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检索条件"任意字段=Proceedings of the 27th ACM symposium on Parallelism in Algorithms and Architectures"

共 54 条记录，以下是11-20 订阅

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM symposium on parallelism in algorithms and archit...

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30th acm symposium on parallelism in algorithms and architectures, SPAA 2018

ISBN: (纸本)9781450357999

the proceedings contain 47 papers. the topics discussed include: parallel minimum cuts in near-linear work and low depth;trees for vertex cuts, hypergraph cuts and minimum hypergraph bisection;dynamic representations of sparse distributed networks: a locality-sensitive approach;constant-depth and subcubic-size threshold circuits for matrix multiplication;integrated model, batch, and domain parallelism in training neural networks;brief announcement: on approximating pagerank locally with sublinear query complexity;brief announcement: coloring-based task mapping for dragonfly systems;brief announcement: parallel transitive closure within 3D crosspoint memory;and lock-free contention adapting search trees.

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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25th acm symposium on parallelism in algorithms and architectures, SPAA 2013

the proceedings contain 39 papers. the topics discussed include: Fast greedy algorithms in MapReduce and streaming;reduced hardware transactions: a new approach to hybrid transactional memory;recursive design of hardware priority queues;drop the anchor: lightweight memory management for non-blocking data structures;scalable statistics counters;storage and search in dynamic peer-to-peer networks;expected sum and maximum of displacement of random sensors for coverage of a domain;on dynamics in selfish network creation;brief announcement: truly parallel burrows-wheeler compression and decompression;brief announcement: locality in wireless scheduling;brief announcement: universally truthful secondary spectrum auctions;and brief announcement: online batch scheduling for flow objectives.

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SPAA'07: proceedings of the Nineteenth Annual symposium on parallelism in algorithms and architectures

SPAA'07: Proceedings of the Nineteenth Annual Symposium on P...

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SPAA'07: 19th Annual symposium on parallelism in algorithms and architectures

ISBN: (纸本)159593667X

the proceedings contain 37 papers. the topics discussed include: on triangulation of simple networks;strong-diameter decompositions of minor free graphs;approximation algorithms for multiprocessor scheduling under uncertainty;scheduling DAGs on asynchronous processors;scheduling to minimize gaps and power consumption;cache-oblivious streaming B-trees;an experimental comparison of cache-oblivious and cache-conscious programs;scheduling threads for constructive cache sharing on CMPs;proximity-aware directory-based coherence for multi-core processor architectures;a parallel dynamic programming algorithm on a multi-core architecture;tight bounds for distributed selection;local MST computation with short advice;distributed approximation of capacitated dominating sets;packing to angles and sectors;and the notion of a timed register and its application to indulgent synchronization.

关键词： Computer programming

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

ISBN: (纸本)9781450342100

the proceedings contain 52 papers. the topics discussed include: randomized approximate nearest neighbor search with limited adaptivity;encoding short ranges in TCAM without expansion: efficient algorithm and applications;extending the nested parallel model to the nested dataflow model with provably efficient schedulers;latency-hiding work stealing: scheduling interacting parallel computations with work stealing;provably good and practically efficient parallel race detection for fork-join programs;dynamic determinacy race detection for task parallelism with futures;RUBIC: online parallelism tuning for co-located transactional memory applications;investigating the performance of hardware transactions on a multi-socket machine;parallel algorithms for asymmetric read-write costs;general profit scheduling and the power of migration on heterogeneous machines;the power of migration in online machine minimization;fair online scheduling for selfish jobs on heterogeneous machines;scheduling parallelizable jobs online to minimize the maximum flow time;clairvoyant dynamic bin packing for job scheduling with minimum server usage time;parallel equivalence class sorting: algorithms, lower bounds, and distribution-based analysis;and parallel approaches to the string matching problem on the GPU.

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Register file port requirements of transport triggered architectures 27

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27th Annual International symposium on Microarchitecture, MICRO 1994

作者： Hoogerbrugge, Jan Corporaal, Henk Delft University of Technology Department of Electrical Engineering P.O. Box 5031 GA Delft2600 Netherlands

ISBN: (纸本)0897917073

Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units;this connectivity is expensive and increases the cycle time. this paper shows that the new class of transport triggered architectures requires fewer ports on the shared register file than traditional operation triggered architectures. this is achieved by programming data-transports instead of operations. Experiments with our extended basic block scheduler have shown that the reduction of the required number of register file ports is substantial. the average requirement for scalar applications is 0.50 read and 0.35 write ports per operation instead of 2 read and 1 write ports. Due to this reduction it is possible to execute 2 operations per cycle with a two-ported register file and 3.6 operations per cycle with a six-ported register file. © 1994 acm.

关键词： Architecture

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Dopia: Online parallelism Management for Integrated CPU/GPU architectures 22

Dopia: Online Parallelism Management for Integrated CPU/GPU ...

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27th acm SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Cho, Younghyun Park, Jiyeon Negele, Florian Jo, Changyeon Gross, thomas R. Egger, Bernhard Univ Calif Berkeley Berkeley CA 94720 USA Seoul Natl Univ Seoul South Korea Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781450392044

Recent desktop and mobile processors often integrate CPU and GPU onto the same die. the limited memory bandwidth of these integrated architectures can negatively affect the performance of data-parallel workloads when all computational resources are active. the combination of active CPU and GPU cores achieving the maximum performance depends on a workload's characteristics, making manual tuning a time-consuming task. Dopia is a fully automated framework that improves the performance of data-parallel workloads by adjusting the Degree Of parallelism on Integrated architectures. Dopia transparently analyzes and rewrites OpenCL kernels before executing them with the number of CPU and GPU cores expected to yield the best performance. Evaluated on AMD and Intel integrated processors, Dopia achieves 84% of the maximum performance attainable by an oracle.

关键词： parallelism management integrated architectures code analysis machine learning

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Brief Announcement: Meeting the Challenges of Parallelizing Sequential Programs 17

Brief Announcement: Meeting the Challenges of Parallelizing ...

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29th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Atre, Rohit Jannesari, Ali Wolf, Felix Tech Univ Darmstadt Darmstadt Germany Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450345934

Discovering which code sections in a sequential program can be made to run in parallel is the first step in parallelizing it, and programmers routinely struggle in this step. Most of the current parallelism discovery techniques focus on specific language constructs while trying to identify such code sections. In contrast, we propose to concentrate on the computations performed by a program. In our approach, a program is treated as a collection of computations communicating with one another using a number of variables. Each computation is represented as a Computational Unit (CU). A CU contains the inputs and outputs of a computation, and the three phases of a computation: read, compute, and write. Based on the notion of CU, We present a unified framework to identify both loop and task parallelism in sequential programs.

关键词： parallelism discovery multicore architectures static analysis task parallelism profiling

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Brief Announcement: Parallelization of Asynchronous Variational Integrators for Shared Memory architectures

Brief Announcement: Parallelization of Asynchronous Variatio...

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26th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Hassaan, M. Amber Nguyen, Donald Pingali, Keshav Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA Univ Texas Austin Dept Comp Sci Austin TX 78712 USA

ISBN: (纸本)9781450328210

Asynchronous variational integrators (AVIs) are used in computational mechanics and graphics to solve complex contact mechanics problems. the parallelization of AVI is a difficult problem because it is not possible to build a dependence graph for AVI either at compile-time or at runtime. However, we show that if the dependence graph for AVI can be updated incrementally as the computation is performed, it is possible to parallelize AVI in a systematic way. Using this approach, we are able to obtain speedups of up to 20 on 24 cores for relatively small AVI problems.

关键词： asynchronous variational integrators dependence graph scheduling

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SuperMatrix Out-of-Order Scheduling of Matrix Operations for SMP and Multi-Core architectures 07

SuperMatrix Out-of-Order Scheduling of Matrix Operations for...

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19th Annual symposium on parallelism in algorithms and architectures

作者： Chan, Ernie Quintana-Orti, Enrique S. Quintana-Orti, Gregorio van de Geijn, Robert Univ Texas Austin Dept Comp Sci Austin TX 78712 USA Univ Jaume 1 Dept Ingn & Ciencia Computad Castellon de La Plana Spain

ISBN: (纸本)9781595936677

We discuss the high-performance parallel implementation and execution of dense linear algebra matrix operations on SMP architectures;with an eye towards multi-core processors with many cores. We argue that traditional implementations, as those incorporated in LAPACK, cannot be easily modified to render high performance as well as scalability on these architectures. the solution we propose is to arrange the data structures and algorithms so that matrix blocks become the fundamental units of data;and operations on these blocks become the fundamental units of computation, resulting in algorithms-by-blocks as opposed to the snore traditional blocked algorithms. We show that this facilitates the adoption of techniques akin to dynamic scheduling and out-of-order execution usual in superscalar processors;which we name SuperMatrix Out-of-Order scheduling. Performance results on a 16 CPU Itanium2-based server are used to highlight opportunities and issues related to this new approach.

关键词： data affinity data-flow parallelism dense linear algebra libraries dynamic scheduling out-of-order execution

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Brief Announcement: Wait-free Programming for General Purpose Computations on Graphics Processors

Brief Announcement: Wait-free Programming for General Purpos...

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27th Annual acm symposium on Principles of Distributed Computing

作者： Ha, Phuong H. Tsigas, Philippas Anshus, Otto J. Univ Tromso N-9001 Tromso Norway Tsigas Chamers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781595939890

this paper aims at bridging the gap between the lack of synchronization mechanisms in recent graphics processor (GPU) architectures and the need of synchronization mechanisms in parallel applications. Based on the intrinsic features of recent GPU architectures, we construct strong synchronization objects like wait-free and t-resilient read-modify-write objects for a general model of recent GPU architectures without strong hardware synchronization primitives like test-and-set and compare-and-swap. Accesses to the new wait-free objects have time complexity O(N), where N is the number of concurrent processes. the wait-free objects have space complexity O(N-2): which is optimal. Our result demonstrates that it is possible to construct wait-free synchronization mechanisms for GPUs without the need of strong synchronization primitives in hardware and that wait-free programming is possible for GPUs.

关键词： consensus read-modify-write objects synchronization many-core architectures graphics processors

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