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检索条件"任意字段=Proceedings of the 27th ACM symposium on Parallelism in Algorithms and Architectures"

共 54 条记录，以下是21-30 订阅

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HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing architectures 22

HybriDS: Cache-Conscious Concurrent Data Structures for Near...

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34th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Choe, Jiwon Crotty, Andrew Moreshet, Tali Herlihy, Maurice Bahar, R. Iris Brown Univ Providence RI 02912 USA Northwestern Univ Evanston IL USA

ISBN: (纸本)9781450391467

In recent years, the ever-increasing impact of memory access bottlenecks has brought forth a renewed interest in near-memory processing (NMP) architectures. In this work, we propose and empirically evaluate hybrid data structures, which are concurrent data structures custom-designed for these new NMP architectures. We focus on cache-optimized data structures, such as skiplists and B+ trees, that are often used as index structures in online transaction processing (OLTP) systems to enable fast key-based lookups. these data structures are hierarchical, where lookups begin at a small number of top-level nodes and diverge to many different node paths as they move down the hierarchy, such that nodes in higher levels benefit more from caching. Our proposed hybrid data structures split traditional hierarchical data structures into a host-managed portion consisting of higher-level nodes and an NMP-managed portion consisting of the remaining lower-level nodes, thus retaining and further enhancing the cache-conscious optimizations of their conventional implementations. Although the idea might seem relatively simple, the splitting of the data structure prompts new synchronization problems, and careful implementation is required to ensure high concurrency and correctness. We provide implementations of a hybrid skiplist and a hybrid B+ tree, and we empirically evaluate them on a cycle-accurate full-system architecture simulator. Our results show that the hybrid data structures have the potential to improve performance by more than 2x compared to state-of-the-art concurrent data structures.

关键词： near-memory processing concurrent data structures

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Proximity-Aware Directory-based Coherence for Multi-core Processor architectures 07

Proximity-Aware Directory-based Coherence for Multi-core Pro...

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19th Annual symposium on parallelism in algorithms and architectures

作者： Brown, Jeffery A. Kumar, Rakesh Tullsen, Dean Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)9781595936677

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. this is exacerbated by the fact that interconnection speeds are not scaling well with technology. this paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores. these techniques exploit the differences in geometry between chip multiprocessors and traditional multiprocessor architectures. Directory-based protocols have been proposed as a scalable alternative to snoop-based protocols. In this paper, we discuss implementations of coherence for CMPs and propose and evaluate a novel directory-based coherence scheme to improve the performance of parallel programs on such processors. Proximity-aware coherence accelerates read and write misses by initiating cache-to-cache transfers from the spatially closest sharer. this has the dual benefit of eliminating unnecessary accesses to off-Chip memory, and minimizing the distance over which communicated data moves across the network. the proposed schemes result in speedups up to 74.9% for our workloads.

关键词： Chip Multiprocessors Coherence

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A memory energy consumption analysis of Motion Estimation algorithms using data reuse in video coding systems 14

A memory energy consumption analysis of Motion Estimation al...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Amaral, Livia Silveira, Dieison Povala, Guilherme Agostini, Luciano Porto, Marcelo Zatt, Bruno Group of Architectures and Integrated Circuits - GACI Federal University of Pelotas - UFPel Brazil

ISBN: (纸本)9781479968732

the number of accesses Motion Estimation requires to write and read large amount of data from external memory is the major issue in video coding systems, since, besides being the performance bottleneck of these systems, it impacts directly on the energy consumption. To attenuate this problem, there are solutions that involve data reuse strategies using on-chip SRAM memories. the main advantage of these solutions is the fact that they can achieve high external memory bandwidth reduction on reading operations. this paper presents an evaluation of the impact of the memory accesses and energy consumption considering a Level C+ data reuse scheme for four different fast algorithms and the Full Search algorithm. Our results show that the energy consumption for the traditional method, when no memory bandwidth reduction strategy is used, becomes impractical for most of the considered Motion Estimation algorithms. However, when the data reuse scheme Level C+ is used, the energy consumption related to the memory suffers a great reduction, making it possible for fast algorithms to be used in real-time video coding systems. the reduction reached is up to 97% when considering fast Motion Estimation algorithms. © 2014 IEEE.

关键词： Energy utilization

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DAG3: A tool for design and analysis of applications for multicore architectures 12

DAG3: A tool for design and analysis of applications for mul...

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27th Annual acm symposium on Applied Computing, SAC 2012

作者： Drago, Mauro Luigi Bishop, Judith Politecnico di Milano - DEI Piazza L. Da Vinci 32 20133 Milano Italy Microsoft Research One Microsoft Way Redmond WA 98033 United States

ISBN: (纸本)9781450308571

Despite the availability of libraries and constructs in modern programming languages to support the development of parallel applications, achieving the desired performance improvement can still be difficult. Design patterns and idioms simplify writing of applications but, if they are not applied correctly, the introduced overhead may overwhelm the benefits of parallelism. Performance and parallelism deserve specific software engineering techniques in order to be successfully accounted. In this sense, software design and performance analysis techniques represent a valid option to discover problems in the early stages of development and manage them in an structured manner. In this paper we present Dag3: a tool and a methodology leveraging Direct Acyclic Graphs to design parallel applications and to analyze their performance. Parallel applications are designed by specifying the constituents of the computation, their organization, and their contribution to performance. Parametric analyses can be conducted to estimate performance metrics, such as speedup, and to the identify the critical parts of a computation. To increase programmers' productivity, models can be also used to generate part of the application source code. © 2012 acm.

关键词： Software design

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Energy-efficient Hadamard-based SATD architectures 14

Energy-efficient Hadamard-based SATD architectures

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Cancellier, Luiz Henrique Brascher, Andre Beims Seidel, Ismael Guntzel, Jose Luis Florianópolis Brazil

ISBN: (纸本)9781479968732

In this paper we present energy-efficient Hadamard-based Sum of Absolute Transformed Differences (SATD) architectures. We relied on two state of the art methods for SATD, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. those were combined with architectural decisions, as the use of a transpose buffer. A total of six Hadamard-based SATD architectures were synthesized for a commercial 45 nm standard cell library. the best energy results are related to TE-SATD architectures: down to 7.62 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are achieved when both methods are applied to the transpose buffer base architecture: nearly 10 pJ/SATD with up to 71% smaller area compared with parallel base architectures. © 2014 IEEE.

关键词： Energy efficiency

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Removing the Reliance on Perimeters for Security using Network Views 22

Removing the Reliance on Perimeters for Security using Netwo...

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27th acm symposium on Access Control Models and Technologies (SacmAT)

作者： Anjum, Iffat Kostecki, Daniel Leba, Ethan Sokal, Jessica Bharambe, Rajit Enck, William Nita-Rotaru, Cristina Reaves, Bradley NC State Univ Raleigh NC 27695 USA Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781450393577

Traditional enterprise security relies on network perimeters to define and enforce network security policies. Emerging application-focused Zero Trust architectures attempt to address this long-standing challenge by moving business applications to the cloud and performing enhanced identity and access control checks within a web gateway. However, these solutions ignore the security needs of workstations, development servers, and device management interfaces. In this work, we propose Network Views (abbrev. NetViews) for least-privilege network access control where each host has a different, limited view of the other hosts and services within a network. We present an SDN-based design and demonstrate that our implementation has network latency and throughput comparable to baseline reactive forwarding. We further provide an optimization for multi-connection flows that significantly reduces both redundant access control checks and forwarding state storage in switches. As such, NetViews provides a practical primitive for removing the reliance on security perimeters within enterprise networks.

关键词： enterprise network security zero trust architectures software-defined networking least-privilege

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A knowledge-based framework for reference architectures 12

A knowledge-based framework for reference architectures

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27th Annual acm symposium on Applied Computing, SAC 2012

作者： Nakagawa, Elisa Yumi Becker, Martin Maldonado, José Carlos University of São Paulo - USP PO Box 668 13560-970 São Carlos SP Brazil Fraunhofer IESE Fraunhofer-Platz 1 67663 Kaiserslautern Germany

ISBN: (纸本)9781450308571

Software architectures play a major role in determining system quality, since they form the backbone of any successful software-intensive system. In this context, reference architectures refer to a special type of software architecture that capture the essence of the system architectures of a given domain, encompassing the knowledge about how to develop, standardize, and evolve systems of that domain. However, in spite of the considerable number of reference architectures available, no good understanding exists regarding knowledge contained in reference architectures. the main contribution of this work is to provide a better understanding of such knowledge and to propose a framework which presents a comprehensive panorama of this knowledge. An analysis of this framework is presented based on a relevant, well-known reference architecture widely used in industry. As its main result, this framework could provide a better understanding of the contents of such architectures, enabling the development of more complete, efficient reference architectures. © 2012 acm.

关键词： Software architecture

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HiDP: A Hierarchical Data Parallel Language

HiDP: A Hierarchical Data Parallel Language

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11th IEEE/acm International symposium on Code Generation and Optimization (CGO)

作者： Zhang, Yongpeng Mueller, Frank N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781467355254;9781467355247

Problem domains are commonly decomposed hierarchically to fully utilize parallel resources in modern microprocessors. Such decompositions can be provided as library routines, written by experienced experts, for general algorithmic patterns. But such APIs tend to be constrained to certain architectures or data sizes. Integrating them with application code is often an unnecessarily daunting task, especially when these routines need to be closely coupled with user code to achieve better performance. this paper contributes HiDP, a high-level hierarchical data parallel language. the purpose of HiDP is to improve the coding productivity of integrating hierarchical data parallelism without significant loss of performance. HiDP is a source-to-source compiler that converts a very concise data parallel language into CUDA C++ source code. Internally, it performs necessary analysis to compose user code with efficient and architecture-aware code snippets. this paper discusses various aspects of HiDP systematically: the language, the compiler and the run-time system with built-in tuning capabilities. they enable HiDP users to express algorithms in less code than low-level SDKs require for native platforms. HiDP also exposes abundant computing resources of modern parallel architectures. Improved coding productivity tends to come with a sacrifice in performance. Yet, experimental results show that the generated code delivers performance very close to handcrafted native GPU code.

关键词： C++ language application program interfaces graphics processing units microprocessor chips parallel architectures parallel languages program compilers source coding

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proceedings of the acm Great Lakes symposium on VLSI, GLSVLSI

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLS...

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27th Great Lakes symposium on VLSI, GLSVLSI 2017

ISBN: (纸本)9781450349727

the proceedings contain 89 papers. the topics discussed include: LightNN: filling the gap between conventional deep neural networks and binarized networks;design of a flash-based circuit for multi-valued logic;PreNoc: neural network based predictive routing for network-on-chip architectures;a domain-specific language and compiler for computation-in-memory skeletons;energy efficient in-memory computing platform based on 4-terminal spin hall effect-driven domain wall motion devices;leveraging dual-mode magnetic crossbar for ultra-low energy in-memory data encryption;evaluating data resilience in CNNs from an approximate memory perspective;and a robust C-element design with enhanced metastability performance.

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Achilles' Heel of Plug-and-Play Software architectures: A Grounded theory Based Approach 2019

Achilles' Heel of Plug-and-Play Software Architectures: A Gr...

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27th acm Joint Meeting on European Software Engineering Conference (ESEC) / symposium on the Foundations of Software Engineering (FSE)

作者： Santos, Joanna C. S. Sejfia, Adriana Corrello, Taylor Gadenkanahalli, Smruthi Mirakhorli, Mehdi Rochester Inst Technol Rochester NY 14623 USA

ISBN: (纸本)9781450355728

through a set of well-defined interfaces, plug-and-play architectures enable additional functionalities to be added or removed from a system at its runtime. However, plug-ins can also increase the application's attack surface or introduce untrusted behavior into the system. In this paper, we (1) use a grounded theory-based approach to conduct an empirical study of common vulnerabilities in plug-and-play architectures;(2) conduct a systematic literature survey and evaluate the extent that the results of the empirical study are novel or supported by the literature;(3) evaluate the practicality of the findings by interviewing practitioners with several years of experience in plug-and-play systems. By analyzing Chromium, thunderbird, Firefox, Pidgin, WordPress, Apache OfBiz, and OpenMRS, we found a total of 303 vulnerabilities rooted in extensibility design decisions and observed that these plugin-related vulnerabilities were caused by 16 different types of vulnerabilities. Out of these 16 vulnerability types we identified 19 mitigation procedures for fixing them. the literature review supported 12 vulnerability types and 8 mitigation techniques discovered in our empirical study, and indicated that 5 mitigation techniques were not covered in our empirical study. Furthermore, it indicated that 4 vulnerability types and 11 mitigation techniques discovered in our empirical study were not covered in the literature. the interviews with practitioners confirmed the relevance of the findings and highlighted ways that the results of this empirical study can have an impact in practice.

关键词： Software Security Plug-and-Play Design Vulnerabilities

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