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检索条件"任意字段=Proceedings of the 27th ACM symposium on Parallelism in Algorithms and Architectures"

共 54 条记录，以下是31-40 订阅

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Implementing a Blocked Aasen's Algorithm with a Dynamic Scheduler on Multicore architectures

Implementing a Blocked Aasen's Algorithm with a Dynamic Sche...

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IEEE 27th International Parallel and Distributed Processing symposium (IPDPS)

作者： Ballard, Grey Becker, Dulceneia Demmel, James Dongarra, Jack Druinsky, Alex Peled, Inon Schwartz, Oded Toledo, Sivan Yamazaki, Ichitaro Univ Tennessee Knoxville TN 37996 USA Tel Aviv Univ IL-69978 Tel Aviv Israel Univ Calif Berkeley Berkeley CA USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9780769549712

Factorization of a dense symmetric indefinite matrix is a key computational kernel in many scientific and engineering simulations. However, there is no scalable factorization algorithm that takes advantage of the symmetry and guarantees numerical stability through pivoting at the same time. this is because such an algorithm exhibits many of the fundamental challenges in parallel programming like irregular data accesses and irregular task dependencies. In this paper, we address these challenges in a tiled implementation of a blocked Aasen's algorithm using a dynamic scheduler. To fully exploit the limited parallelism in this left-looking algorithm, we study several performance enhancing techniques;e. g., parallel reduction to update a panel, tall-skinny LU factorization algorithms to factorize the panel, and a parallel implementation of symmetric pivoting. Our performance results on up to 48 AMD Opteron processors demonstrate that our implementation obtains speedups of up to 2.8 over MKL, while losing only one or two digits in the computed residual norms.

关键词： information retrieval matrix decomposition multiprocessing systems numerical stability parallel architectures parallel programming scheduling

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Towards a colored reflective Petri-net approach to model self-evolving service-oriented architectures 12

Towards a colored reflective Petri-net approach to model sel...

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27th Annual acm symposium on Applied Computing, SAC 2012

作者： Liu, Ying Cazzola, Walter Zhang, Bin Northeastern University Liaoning China DICo Università di Milano Milano Italy

ISBN: (纸本)9781450308571

Service-based software systems could require to evolve during their execution. To support this, we need to consider system evolving since the design phase. Reflective Petri nets separate the system from its evolution by describing it and how it can evolve. However, reflective Petri nets have some expressivity limits and render overcomplicated the consistency checking necessary during service evolution. In this paper, we extend the reflective Petri nets approach to overcome such limits and show that on a case study. © 2012 acm.

关键词： Web services

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Intra-Clustering: Accelerating On-Chip Communication for Data Parallel architectures 27

Intra-Clustering: Accelerating On-Chip Communication for Dat...

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IEEE 27th International symposium on Computer Architecture and High Performance Computing

作者： Yuan, Wen Boyapati, Rahul Wang, Lei Jang, Hyunjun Jin, Yuho Yum, Ki Hwan Kim, Eun Jung Samsung Austin Res Ctr Austin TX 78730 USA Texas A&M Univ College Stn TX 77843 USA Yahoo Inc Sunnyvale CA USA New Mexico State Univ Las Cruces NM 88003 USA

ISBN: (纸本)9781467386210

Modern computation workloads contain abundant Data Level parallelism(DLP), which requires specialized data parallel architectures, such as Graphics Processing Units(GPUs). With parallel programming models, such as CUDA and OpenCL, GPUs are easily to be programmed for non-graphics applications, and therefore become a cost-effective approach for data parallel architectures. the large quantity of available parallelism places a heavy stress on the memory system as the limited number of pins confines the number of memory controllers on the chip. this creates a potential bottleneck for performance scalability of the GPUs. To accelerate communication with the memory system, we propose the Intra-Clustering on-chip network for data parallel architectures, which is built upon a traditional two-dimensional electrical mesh network with memory controllers connected through a nanophotonic ring and compute cores grouped into different clusters. Our evaluations with CUDA benchmarks show that the Intra-Clustering architecture can improve communication delay by an average of 17%(up to 32%) and IPC by an average of 5%(up to 11.5%).

关键词： Cost effectiveness

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Digest of Papers - 27th Annual International symposium on Fault-Tolerant Computing, FTCS 1997

Digest of Papers - 27th Annual International Symposium on Fa...

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27th Annual International symposium on Fault-Tolerant Computing, FTCS 1997

ISBN: (纸本)0818678313

the proceedings contain 42 papers. the topics discussed include: managing dependencies - a key problem in fault-tolerant distributed algorithms;an approach to fault-tolerant parallel processing on intermittently idle, heterogeneous workstations;renegotiable quality of service - a new scheme for fault tolerance in wireless networks;evaluation of a 32-bit microprocessor with built-in concurrent error-detection;probabilistic checkpointing;portable checkpointing for heterogenous architectures;a communication-induced checkpointing protocol that ensures rollback-dependency trackability;a method to automate user interface testing using variable finite state machines;towards a statistical approach to testing object-oriented programs;and experimental evaluation of failure-detection schemes in real-time communication networks.

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proceedings - symposium on Computer Architecture and High Performance Computing

Proceedings - Symposium on Computer Architecture and High Pe...

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IEEE 27th International symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2015

ISBN: (纸本)9781467386210

the proceedings contain 20 papers. the topics discussed include: using hardware transactional memory to enable speculative trace optimization;energy consumption and scalability evaluation for software transactional memory on a real computing environment;replicating the performance evaluation of an n-body application on a manycore accelerator;characterizing anomalies of a multicore ARMv7 cluster with parallel N-body simulations;MDACCER: modified distributed assessment of the closeness CEntrality ranking in complex networks for massively parallel environments;intra-clustering: accelerating on-chip communication for data parallel architectures;Kanga: a skeleton-based generic interface for parallel programming;painless parallelism on heterogeneous hardware leveraging the functional paradigm;CHAOS-MCAPI: an optimized mechanism to support multicore parallel programming;and exploiting parallelism in linear algebra kernels through dataflow execution.

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Convergence and Scalarization for Data-Parallel architectures

Convergence and Scalarization for Data-Parallel Architecture...

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11th IEEE/acm International symposium on Code Generation and Optimization (CGO)

作者： Lee, Yunsup Krashinsky, Ronny Grover, Vinod Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781467355254;9781467355247

Modern throughput processors such as GPUs achieve high performance and efficiency by exploiting data parallelism in application kernels expressed as threaded code. One draw-back of this approach compared to conventional vector architectures is redundant execution of instructions that are common across multiple threads, resulting in energy inefficiency due to excess instruction dispatch, register file accesses, and memory operations. this paper proposes to alleviate these overheads while retaining the threaded programming model by automatically detecting the scalar operations and factoring them out of the parallel code. We have developed a scalarizing compiler that employs convergence and variance analyses to statically identify values and instructions that are invariant across multiple threads. Our compiler algorithms are effective at identifying convergent execution even in programs with arbitrary control flow, identifying two-thirds of the opportunity captured by a dynamic oracle. the compile-time analysis leads to a reduction in instructions dispatched by 29%, register file reads and writes by 31%, memory address counts by 47%, and data access counts by 38%.

关键词： CUDA GPU Scalarization

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A Framework with Cloud Integration for CNN Acceleration on FPGA Devices 32

A Framework with Cloud Integration for CNN Acceleration on F...

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27th International Heterogeneity in Computing Workshop in conjunction with 32nd IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Raspa, Niccolo Natale, Giuseppe Bacis, Marco Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Via Ponzio 34-5 Milan Italy

ISBN: (纸本)9781538655559

the recent years have seen a rapid diffusion of deep learning algorithms as Convolutional Neural Networks (CNNs), and as a consequence, an intensification of industrial and academic research focused on optimizing their implementation. Different computing architectures have been explored, and among all of them, FPGAs seem to be a very attractive choice, since they can deliver sustained performance with high power efficiency, as CNNs can be directly mapped onto hardware, and still offer flexibility thanks to their programmability. In this paper, we present an end-to-end framework to implement CNNs using a dataflow acceleration methodology. the resulting spatial accelerator can be scaled in size if enough resources are available and can exploit both intra- and inter-layers parallelism. We integrate the proposed framework with the deep learning engine Caffe, meaning that we are able to generate the accelerator starting from a Caffe model. We also provide cloud integration of such framework, enabling users to synthesize and deploy the accelerator on the Amazon F1 instances.

关键词： Convolutional Neural Networks Dataflow architectures Cloud-based acceleration FPGA

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PARALLEL algorithms AND architectures FOR RULE-BASED SYSTEMS.

PARALLEL ALGORITHMS AND ARCHITECTURES FOR RULE-BASED SYSTEMS...

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13th Annual International symposium on Computer Architecture - Conference proceedings.

作者： Gupta, Anoop Forgy, Charles Newell, Allen Wedig, Robert Carnegie-Mellon Univ Pittsburgh PA USA Carnegie-Mellon Univ Pittsburgh PA USA

ISBN: (纸本)081860719X

Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from parallelism is quite limited, less than 10-fold. the reasons for the small speedup are: (1) the small number of rules relevant to each change to data memory;(2) the large variation in the processing required by the relevant rules;and (3) the small number of changes made to data memory between synchronization steps. To obtain this limited factor of 10-fold speedup, it is necessary to exploit parallelism at a very fine granularity. It is suggested that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/s. this speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

关键词： Computer systems, Digital

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Hardware/software debugging of large scale many-core architectures 14

Hardware/software debugging of large scale many-core archite...

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27th symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Friederich, Stephanie Heisswolf, Jan Becker, Jurgen Karlsruhe Institute of Technology Germany

ISBN: (纸本)9781479968732

the size of current multi-processor system-on-chip (MPSoC) is growing unsustainable. Besides, new decentralized software approaches are being developed to handle the management of increasing resources. To verify the system functionality of these novel hardware/software systems, sufficiently accurate models are required. However, current simulation tools have limited scalability and performance;hence hardware prototypes and debugging concepts are necessary for system verification. We present a novel debug approach which offers visualization of hardware/software interaction for system level verification. the debug concept comprises debug probes within each router of the network as well as monitoring units to trace the activity of each core in the MPSoC. In addition a transactor based method is proposed to transmit the huge amount of debug information out of the hardware prototype to evaluate the information on a standard host computer. Experimental results show that the resource overhead is insignificant in contrast to the gain of extensive debug possibilities. Furthermore the number of pins required for the presented debugging concept is kept constant independent of the architecture size and thus we are not facing problems of limited debug interfaces or pins. In comparison to conventional debugging we show improvements in scalability and bandwidth. © 2014 IEEE.

关键词： Network-on-chip

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Statistical scalability analysis of communication operations in distributed applications 01

Statistical scalability analysis of communication operations...

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8th acm SIGPLAN symposium on the Principles and Practice of Parallel Computing

作者： Vetter, JS McCracken, MO Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781581133462

Current trends in high performance computing suggest that users will soon have widespread access to clusters of multiprocessors with hundreds, if not thousands, of processors. this unprecedented degree of parallelism will undoubtedly expose scalability limitations in existing applications, where scalability is the ability of a parallel algorithm on a parallel architecture to effectively utilize an increasing number of processors. Users will need precise and automated techniques for detecting the cause of limited scalability. this paper addresses this dilemma. First, we argue that users face numerous challenges in understanding application scalability: managing substantial amounts of experiment data, extracting useful trends from this data, and reconciling performance information with their application's design. Second, we propose a solution to automate this data analysis problem by applying fundamental statistical techniques to scalability experiment data. Finally, we evaluate our operational prototype on several applications, and show that statistical techniques offer an effective strategy for assessing application scalability. In particular, we find that non-parametric correlation of the number of tasks to the ratio of the time for communication operations to overall communication time provides a reliable measure for identifying communication operations that scale poorly.

关键词： Scalability Experimental data statistical techniques Consumers Communication Research Automated recording Parallel architectures Surgery Multiprocessor High Performance Computing Parallel algorithms

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