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Detecting Numerical Bugs in Neural Network architectures 2020

Detecting Numerical Bugs in Neural Network Architectures

引用

28th acm Joint Meeting on European Software Engineering Conference and symposium on the Foundations of Software Engineering (ESEC/FSE)

作者： Zhang, Yuhao Ren, Luyao Chen, Liqian Xiong, Yingfei Cheung, Shing-Chi Xie, Tao Peking Univ MoE Dept Comp Sci & Technol Key Lab High Confidence Software Technol Beijing Peoples R China Natl Univ Def Technol Key Lab Software Engn Complex Syst Coll Comp Changsha Peoples R China Hong Kong Univ Sci & Technol Dept Comp Sci & Engn Hong Kong Peoples R China

ISBN: (纸本)9781450370431

Detecting bugs in deep learning software at the architecture level provides additional benefits that detecting bugs at the model level does not provide. this paper makes the first attempt to conduct static analysis for detecting numerical bugs at the architecture level. We propose a static analysis approach for detecting numerical bugs in neural architectures based on abstract interpretation. Our approach mainly comprises two kinds of abstraction techniques, i.e., one for tensors and one for numerical values. Moreover, to scale up while maintaining adequate detection precision, we propose two abstraction techniques: tensor partitioning and (elementwise) affine relation analysis to abstract tensors and numerical values, respectively. We realize the combination scheme of tensor partitioning and affine relation analysis (together with interval analysis) as DEBAR, and evaluate it on two datasets: neural architectures with known bugs (collected from existing studies) and real-world neural architectures. the evaluation results show that DEBAR outperforms other tensor and numerical abstraction techniques on accuracy without losing scalability. DEBAR successfully detects all known numerical bugs with no false positives within 1.7-2.3 seconds per architecture. On the real-world architectures, DEBAR reports 529 warnings within 2.6-135.4 seconds per architecture, where 299 warnings are true positives.

关键词： Neural Network Static Analysis Numerical Bugs

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM symposium on parallelism in algorithms and archit...

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30th acm symposium on parallelism in algorithms and architectures, SPAA 2018

ISBN: (纸本)9781450357999

the proceedings contain 47 papers. the topics discussed include: parallel minimum cuts in near-linear work and low depth;trees for vertex cuts, hypergraph cuts and minimum hypergraph bisection;dynamic representations of sparse distributed networks: a locality-sensitive approach;constant-depth and subcubic-size threshold circuits for matrix multiplication;integrated model, batch, and domain parallelism in training neural networks;brief announcement: on approximating pagerank locally with sublinear query complexity;brief announcement: coloring-based task mapping for dragonfly systems;brief announcement: parallel transitive closure within 3D crosspoint memory;and lock-free contention adapting search trees.

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A Study on Markovian and Deep Learning Based architectures for Household Appliance-level Load Modeling and Recognition 28

A Study on Markovian and Deep Learning Based Architectures f...

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28th IEEE International symposium on Industrial Electronics (IEEE-ISIE)

作者： Hosseini, S. Henao, N. Kelouwani, S. Agbossou, K. Cardenas, A. Univ Quebec Trois Rivieres Dept Elect & Comp Engn Trois Rivieres PQ G9A 5H7 Canada Univ Quebec Trois Rivieres Dept Mech Engn Trois Rivieres PQ G9A 5H7 Canada Univ Quebec Trois Rivieres Hydrogen Res Inst Trois Rivieres PQ G9A 5H7 Canada

ISBN: (纸本)9781728136660

the promise of non-intrusive approach of Appliance Load Monitoring (ALM) promotes the load decomposition analysis at the most disaggregated level. Accordingly, appliance-level load modeling is bolstered to provide appliance-level information and quantify energy consumption. this paper intends to investigate the proficiency of Markovian models, as the state-of-the-art and Deep Learning (DL) architectures, as the cutting-edge of machine learning methods for load modeling through disaggregation practice. Particularly, a simple Recurrent Neural Network (RNN) as a fundamental network architecture for DL is chosen, which is consistent with first-order Markovian chain assumption. A dataset with a challenging load disaggregation case is utilized for the analysis. the same learning mechanism is used to execute the training phase of both approaches, regarding a fair performance comparison. Consequently, the recognition accuracy of the algorithms is evaluated. the results demonstrate that Markov decision procedure is comparable with DL basic manner. Additionally, the paper elaborates remarks on essential prerequisites, specifically data adequacy, to provide a thorough load modeling analysis. From a practical standpoint, this work aims to pinpoint major barriers in terms of both load model construction and recognition towards actual implementation.

关键词： Markov models Deep learning Recurrent neural networks Load modeling Disaggregation

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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29th acm symposium on parallelism in algorithms and architectures, SPAA 2017

ISBN: (纸本)9781450345934

the proceedings contain 45 papers. the topics discussed include: randomized composable coresets for matching and vertex cover;almost optimal streaming algorithms for coverage problems;bicriteria distributed submodular maximization in a few rounds;on energy conservation in data centers;asymptotically optimal approximation algorithms for coflow scheduling;online flexible job scheduling for minimum span;minimizing total weighted flow time with calibrations;brief announcement: scheduling parallelizable jobs online to maximize throughput;brief announcement: a new improved bound for coflow scheduling;and a communication-avoiding parallel algorithm for the symmetric eigenvalue problem.

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Brief Announcement: Meeting the Challenges of Parallelizing Sequential Programs 17

Brief Announcement: Meeting the Challenges of Parallelizing ...

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29th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Atre, Rohit Jannesari, Ali Wolf, Felix Tech Univ Darmstadt Darmstadt Germany Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450345934

Discovering which code sections in a sequential program can be made to run in parallel is the first step in parallelizing it, and programmers routinely struggle in this step. Most of the current parallelism discovery techniques focus on specific language constructs while trying to identify such code sections. In contrast, we propose to concentrate on the computations performed by a program. In our approach, a program is treated as a collection of computations communicating with one another using a number of variables. Each computation is represented as a Computational Unit (CU). A CU contains the inputs and outputs of a computation, and the three phases of a computation: read, compute, and write. Based on the notion of CU, We present a unified framework to identify both loop and task parallelism in sequential programs.

关键词： parallelism discovery multicore architectures static analysis task parallelism profiling

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

ISBN: (纸本)9781450342100

the proceedings contain 52 papers. the topics discussed include: randomized approximate nearest neighbor search with limited adaptivity;encoding short ranges in TCAM without expansion: efficient algorithm and applications;extending the nested parallel model to the nested dataflow model with provably efficient schedulers;latency-hiding work stealing: scheduling interacting parallel computations with work stealing;provably good and practically efficient parallel race detection for fork-join programs;dynamic determinacy race detection for task parallelism with futures;RUBIC: online parallelism tuning for co-located transactional memory applications;investigating the performance of hardware transactions on a multi-socket machine;parallel algorithms for asymmetric read-write costs;general profit scheduling and the power of migration on heterogeneous machines;the power of migration in online machine minimization;fair online scheduling for selfish jobs on heterogeneous machines;scheduling parallelizable jobs online to minimize the maximum flow time;clairvoyant dynamic bin packing for job scheduling with minimum server usage time;parallel equivalence class sorting: algorithms, lower bounds, and distribution-based analysis;and parallel approaches to the string matching problem on the GPU.

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Machine vision inmanufacturing processes and the digital twin ofmanufacturing architectures 28

Machine vision inmanufacturing processes and the digital twi...

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28th DAAAM International symposium on Intelligent Manufacturing and Automation, DAAAM 2017

作者： Deac, Gicu Calin Deac, Crina Narcisa Popa, Cicerone Laurentiu Ghinea, Mihalache Cotet, Costel Emil

ISBN: (纸本)9783902734112

this paper describes some results of authors' research in machine vision, as a key technology, essential in connecting the manufacturing processes with the digital twin of the manufacturing architecture. the focus is on designing a system that uses machine vision in combination with deep learning algorithms. the result is a human-like vision system for realtime analysis and interpretation of all video streams of cameras to continuously detect and count the various products on the production line. All detected features and counting information are available in real-Time by augmenting on a video screen and streamed to the cloud where they can be easily processed and stored.

关键词： Computer vision

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European swaption by monte carlo estimation on modern intel architectures 28

European swaption by monte carlo estimation on modern intel ...

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28th DAAAM International symposium on Intelligent Manufacturing and Automation, DAAAM 2017

作者： Mudnic, Eugen Celar, Stipe Seremet, Zeljko Matic, Filipa

ISBN: (纸本)9783902734112

Modern computing resources provide substantial processing power but require that the programmatic implementation of used numerical algorithms is fine-Tuned to the target CPU architecture. the main performance gains could be obtained minimizing cache traffic and by efficient using of multiple levels of CPU parallel units. Monte Carlo estimation of LIBOR models is an example of challenging computational finance/computer programming problem. this paper compares the efficiency of multicore (Intel Core Haswell) and manycore platforms (Intel Xeon Phi Knight Corner and Intel Xeon Phi Knight Landing) for the calculation European LIBOR-based swaptions. Target optimized programmatic implementations of LIBOR calculation using the Intel Cilk Plus and OpenMP standards are presented and benchmarked. Results show that Intel Xeon Phi Knight Landing evaluate payoff European LIBOR-based swaptions faster, economically profitable and more energy efficient than the Intel Xeon Phi Knight Corner coprocessor and Intel Core Haswell.

关键词： Intelligent systems

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Annual acm symposium on parallelism in algorithms and architectures

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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27th acm symposium on parallelism in algorithms and architectures, SPAA 2015

ISBN: (纸本)9781450335881

the proceedings contain 42 papers. the topics discussed include: sorting with asymmetric read and write costs;myths and misconceptions about threads;new streaming algorithms for parameterized maximal matching & beyond;efficient approximation algorithms for computing k disjoint restricted shortest paths;fast and better distributed MapReduce algorithms for k-center clustering;fair adaptive parallelism for concurrent transactional memory applications;towards a universal approach for the finite departure problem in overlay networks;a compiler-runtime application binary interface for pipe-while loops;the Cilkprof scalability profiler;efficiently detecting races in Cilk programs that use reducer hyperobjects;threadScan: automatic and scalable memory reclamation;temporal fairness of round robin: competitive analysis for Lk-norms of flow time;and space and time efficient parallel graph decomposition, clustering, and diameter approximation.

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proceedings, SBCCI 2015 - 28th symposium on Integrated Circuits and Systems Design: Chip in Bahia

Proceedings, SBCCI 2015 - 28th Symposium on Integrated Circu...

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28th symposium on Integrated Circuits and Systems Design, SBCCI 2015

ISBN: (纸本)9781450337632

the proceedings contain 42 papers. the topics discussed include: system-level design of heterogeneous system-on-chip architectures;designing CMOS for near-threshold minimum-energy operation and extremely wide V-F scaling;SDDS-NCL design: analysis of supply voltage scaling;minimization and encoding of high performance asynchronous state machines based on genetic algorithm;a framework for multi-FPGA interconnection using multi gigabit transceivers;design of high-voltage level shifters based on stacked standard transistors for a wide range of supply voltages;0.5 V supply voltage reference based on the MOSFET ZTC condition;a low-area and high-throughput intra prediction architecture for a multi-standard HEVC and H.264/AVC video encoder;memory-aware and high-throughput hardware design for the HEVC fractional motion estimation;real-time architecture for HEVC motion compensation sample interpolator for UHD videos;and optimum operating points of transistors with minimal aging-aware sensitivity.

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