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SPAA 2014 - proceedings of the 26th acm symposium on parallelism in algorithms and architectures

SPAA 2014 - Proceedings of the 26th ACM Symposium on Paralle...

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26th acm symposium on parallelism in algorithms and architectures, SPAA 2014

ISBN: (纸本)9781450328210

the proceedings contain 42 papers. the topics discussed include: on dynamic bin packing for resource allocation in the cloud;on the online fault-tolerant server consolidation problem;on computing maximal independent sets of hypergraphs in parallel;simple parallel and distributed algorithms for spectral graph sparsification;concurrent data structures for efficient streaming aggregation;provably good scheduling for parallel programs that use data structures through implicit batching;scheduling selfish jobs on multidimensional parallel machines;LP rounding and combinatorial algorithms for minimizing active and busy time;a note on multiprocessor speed scaling with precedence constraints;executing dynamic data-graph computations deterministically using chromatic scheduling;the PCL theorem. transactions cannot be parallel, consistent and live;adaptive integration of hardware and software lock elision techniques;and transaction-friendly condition variables.

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Brief Announcement: Parallelization of Asynchronous Variational Integrators for Shared Memory architectures

Brief Announcement: Parallelization of Asynchronous Variatio...

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26th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Hassaan, M. Amber Nguyen, Donald Pingali, Keshav Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA Univ Texas Austin Dept Comp Sci Austin TX 78712 USA

ISBN: (纸本)9781450328210

Asynchronous variational integrators (AVIs) are used in computational mechanics and graphics to solve complex contact mechanics problems. the parallelization of AVI is a difficult problem because it is not possible to build a dependence graph for AVI either at compile-time or at runtime. However, we show that if the dependence graph for AVI can be updated incrementally as the computation is performed, it is possible to parallelize AVI in a systematic way. Using this approach, we are able to obtain speedups of up to 20 on 24 cores for relatively small AVI problems.

关键词： asynchronous variational integrators dependence graph scheduling

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MIC-SVM: Designing A Highly Efficient Support Vector Machine For Advanced Modern Multi-Core and Many-Core architectures

MIC-SVM: Designing A Highly Efficient Support Vector Machine...

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IEEE 28th International Parallel & Distributed Processing symposium (IPDPS)

作者： You, Yang Song, Shuaiwen Leon Fu, Haohuan Marquez, Andres Dehnavi, Maryam Mehri Barker, Kevin Cameron, Kirk W. Randles, Amanda Peters Yang, Guangwen Tsinghua Univ Ctr Earth Sci Minist Educ Key Lab Earth Syst Modeling Beijing 100084 Peoples R China Tsinghua Univ TNList Beijing Peoples R China Pacific NW Natl Lab Richland WA 02139 USA Harvard Univ MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA Virginia Tech Blacksburg VA USA Lawrence Livermore Natl Lab Livermore CA USA

ISBN: (纸本)9780769552071

Support Vector Machine (SVM) has been widely used in data-mining and Big Data applications as modern commercial databases start to attach an increasing importance to the analytic capabilities. In recent years, SVM was adapted to the field of High Performance Computing for power/performance prediction, auto-tuning, and runtime scheduling. However, even at the risk of losing prediction accuracy due to insufficient runtime information, researchers can only afford to apply offline model training to avoid significant runtime training overhead. Advanced multi-and many-core architectures offer massive parallelism with complex memory hierarchies which can make runtime training possible, but form a barrier to efficient parallel SVM design. To address the challenges above, we designed and implemented MIC-SVM, a highly efficient parallel SVM for x86 based multi-core and many-core architectures, such as the Intel Ivy Bridge CPUs and Intel Xeon Phi co-processor (MIC). We propose various novel analysis methods and optimization techniques to fully utilize the multilevel parallelism provided by these architectures and serve as general optimization methods for other machine learning tools. MIC-SVM achieves 4.4-84x and 18-47x speedups against the popular LIBSVM, on MIC and Ivy Bridge CPUs respectively, for several real-world data-mining datasets. Even compared with GPUSVM, run on a top of the line NVIDIA k20x GPU, the performance of our MIC-SVM is competitive. We also conduct a cross-platform performance comparison analysis, focusing on Ivy Bridge CPUs, MIC and GPUs, and provide insights on how to select the most suitable advanced architectures for specific algorithms and input data patterns.

关键词： Support Vector Machine Multi & Many-Core architectures Parallelization Optimization Techniques Performance Analysis

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A hybrid ILP-CP model for mapping Directed Acyclic Task Graphs to multicore architectures 28

A hybrid ILP-CP model for mapping Directed Acyclic Task Grap...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Emeretlis, Andreas theodoridis, George Alefragis, Panayiotis Voros, Nikolaos Univ Patras Dept Elect & Comp Engn Patras Greece Technol Educ Inst Western Greece Comp & Informat Engn Dept Patras Greece

ISBN: (纸本)9781479941162

Directed Acyclic Task Graphs serve as typical kernel representation for embedded applications. Modern embedded multicore architectures raise new challenges for efficient mapping and scheduling of task DAGs providing a large number of heterogeneous resources. In this paper, a hybrid Integer Linear Programming - Constraint Programming method that uses the Benders decomposition is used to find proven optimal solutions. the proposed method is augmented with cuts generation schemes for accelerating the solution process. Experimental results show that the proposed method systematically outperforms an ILP-based solution method.

关键词： multicore architectures DAG mapping tasks scheduling integer linear programming constraint programming

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SupMR: Circumventing Disk and Memory Bandwidth Bottlenecks for Scale-up MapReduce 28

SupMR: Circumventing Disk and Memory Bandwidth Bottlenecks f...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Sevilla, Michael Nassi, Ike Ioannidou, Kleoni Brandt, Scott Maltzahn, Carlos Univ Calif Santa Cruz Comp Sci Dept Santa Cruz CA 95060 USA

ISBN: (纸本)9781479941162

Reading input from primary storage (i.e. the ingest phase) and aggregating results (i.e. the merge phase) are important pre- and post-processing steps in large batch computations. Unfortunately, today's data sets are so large that the ingest and merge job phases are now performance bottlenecks. In this paper, we mitigate the ingest and merge bottlenecks by leveraging the scale-up MapReduce model. We introduce an ingest chunk pipeline and a merge optimization that increases CPU utilization (50 - 100%) and job phase speedups (1.16x - 3.13x) for the ingest and merge phases. Our techniques are based on well-known algorithms and scale-out MapReduce optimizations, but applying them to a scale-up computation framework to mitigate the ingest and merge bottlenecks is novel.

关键词： Applications architectures Distributed applications Distributed systems Performance measurements

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PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigurable architectures 28

PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigur...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Cattaneo, Riccardo Bellini, Riccardo Durelli, Gianluca Pilato, Christian Santambrogio, Marco D. Sciuto, Donatella Politecn Milan Dipartimento Elettron & Informaz Milan Italy Columbia Univ Dept Comp Sci New York NY 10027 USA

ISBN: (纸本)9781479941162

Harnessing the full capabilities offered by reconfigurable hardware is still a demanding task: the lack of proper methodologies and the intrinsic time consuming and error prone tailoring of these systems around the specific application places a barrier to the adoption of this technology. Partial and Dynamic Reconfiguration (PDR), in this context, is a specific feature whose potential is undiscussed but yet to uncover. In this work, we propose PaRA-Sched, an improvement for a state of the art, highly automated design methodology that allows the designer to rapidly explore the impact of PDR employment during the early stages of the design process. Specifically, we extend the scheduling infrastructure of the framework to explicitly take into account PDR to better explore the design space and improve overall performance by automatically masking reconfiguration time when possible. We show how this additional degree of freedom leads to designs whose performance are improved with respect to the baseline, with a limited increase in time spent during DSE.

关键词： Field Programmable Gate Arrays High Performance Computing Reconfigurable architectures Scheduling algorithms Design methodology

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SmartBricks: A visual environment to design and explore novel custom domain-specific architectures 28

SmartBricks: A visual environment to design and explore nove...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Sistla, AnilKumar Luo, Xiaozhong Malladi, Mukund Reisner, Marc Ganduri, Rajasekhar Mehta, Gayatri Univ North Texas Denton TX 76207 USA Johns Hopkins Univ Baltimore MD 21218 USA

ISBN: (纸本)9781479941162

Custom domain-specific architectures are very promising for creating designs that are highly optimized to the needs of a particular application domain. However, it is extremely difficult to find optimal tradeoffs in designing a new architecture, or even to fully understand the design space. therefore, there is a great need to develop an optimum design framework that allows designers to explore the design space efficiently and identify efficient architectures quickly for an application domain. In this paper, we describe SmartBricks, a highly visual design environment that we have developed for designing and exploring custom domain-specific architectures quickly and efficiently. this game-like design environment will be accessible to a broad community so that even non-engineers and non-scientists can contribute to building and exploring out-of-the-box architectural designs.

关键词： Architectural design

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A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time 28

A Framework for Customizing Virtual 3-D Reconfigurable Platf...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Siozios, Kostas Soudris, Dimitrios Huebner, Michael Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece Ruhr Univ Bochum Bochum Germany

ISBN: (纸本)9781479941162

Existing application domains exhibit variations in terms of complexity, performance and power consumption, whereas their efficient implementation onto general-purpose reconfigurable platforms is not always a viable solution. Towards this goal, throughout this paper, we introduce a software supported framework for supporting efficient customization of these platforms. Rather than similar approaches, where the architectural parameters were defined during the exploration phase (design-time), our solution provides post-fabrication customization of architectural parameters based on application's inherent requirements through a virtualization layer. For evaluation purposes, the introduced framework was applied to 3-D reconfigurable architectures. Experimental results with applications from various domains prove the effectiveness of our solution, as we achieve average delay and power reduction by 1.43x and 1.15x, respectively, as compared to the existing way for application implementation.

关键词： Reconfigurable architectures

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Hardware/Software Vectorization for Closeness Centrality on Multi-/Many-Core architectures 28

Hardware/Software Vectorization for Closeness Centrality on ...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Sariyuce, Ahmet Erdem Saule, Erik Kaya, Kamer Catalyurek, Umit V. Ohio State Univ Dept Biomed Informat Columbus OH 43210 USA Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA Univ N Carolina Dept Comp Sci Charlotte NC 28223 USA

ISBN: (纸本)9781479941162

Centrality metrics have shown to be highly correlated with the importance and loads of the nodes in a network. Given the scale of today's social networks, it is essential to use efficient algorithms and high performance computing techniques for their fast computation. In this work, we exploit hardware and software vectorization in combination with fine-grain parallelization to compute the closeness centrality values. the proposed vectorization approach enables us to do concurrent breadth-first search operations and significantly increases the performance. We provide a comparison of different vectorization schemes and experimentally evaluate our contributions with respect to the existing parallel CPU-based solutions on cutting-edge hardware. Our implementations achieve to be 11 times faster than the state-of-the-art implementation for a graph with 234 million edges. the proposed techniques are beneficial to show how the vectorization can be efficiently utilized to execute other graph kernels that require multiple traversals over a large-scale network on cutting-edge architectures.

关键词： Centrality closeness centrality vectorization breadth-first search Intel Xeon Phi

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Scheduling Methods for Accelerating Applications on architectures with Heterogeneous Cores 28

Scheduling Methods for Accelerating Applications on Architec...

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28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Chen, Linchuan Huo, Xin Agrawal, Gagan Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781479941162

Intra-node architectures for high performance machines have been rapidly evolving over the recent years. We are seeing a diverse set of architectures, most of them with heterogeneous cores. this leads to two important questions for HPC programming: 1) how do we accelerate a single application using a heterogeneous collection of cores? 2) how do we develop applications and runtime systems that maintain portability and performance portability across a diverse set of architectures? By looking at the characteristics of the architectures, we formulate a scheduling problem with non-coherent, non-uniform access shared memory. We have developed several distinct locking free dynamic scheduling methods for such cases, including a master-worker method, a core-level token passing method, and a device-level token passing method. these methods have been implemented on two different architectures: an AMD Fusion APU, and a decoupled CPU-GPU node involving a multi-core CPU and two NVIDIA GPUs, and thus, we provide portability for applications across different types of heterogeneous systems. Using six different applications, we compare different scheduling models against multi-core CPU-only and many-core GPU-only versions. the best CPU+1GPU version has a speedup of between 1.11 and 1.88 over the better of the single device versions. the CPU+2GPU execution further improves the performance by 1.25x to 1.79x over the CPU+1GPU versions. Comparing against the scheduling methods implemented in StarPU and OmpSs, two recent systems for CPU-GPU scheduling, we see 1.08x to 1.21x speedups over the faster of StarPU and OmpSs executions for each application.

关键词： Heterogeneous CPU-GPU architectures Locking-free Scheduling

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