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检索条件"任意字段=Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures"

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Analyzing resource interdependencies in multi-core architectures to improve scheduling decisions 13

Analyzing resource interdependencies in multi-core architect...

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28th Annual acm symposium on Applied Computing, SAC 2013

作者： Busse, Anselm Schönherr, Jan H. Diener, Matthias Mühl, Gero Richling, Jan Technische Universität Berlin Berlin Germany Federal University of Rio Grande do Sul Porto Alegre Brazil University of Rostock Rostock Germany

ISBN: (纸本)9781450316569

Since the advent of multi-core processors, different multi-core system and in particular processor architectures have emerged exhibiting individual advantages and disadvantages. One of the main distinguishing factors among these architectures is their varying degree and type of resource sharing among individual cores. On the one hand, resource sharing is necessary for the cores to communicate, while on the other hand resource sharing is often used for economic reasons. Depending on the degree and type of resource sharing, the impact on performance depends on the workload applied and can vary to a large extend. In this paper, we investigate the impact of different kinds of resource interdependencies found in current processors on the performance of scheduling strategies using a set of benchmarks. Our results show that the architecture has a major impact on the performance of a process placement strategy. However, they also point out that simple strategies taking only a few basic architectural characteristics into account fall short. thus, new holistic scheduling strategies are needed that take more characteristics into account. Copyright 2013 acm.

关键词： Scheduling

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User centric complex event processing based on service oriented architectures 13

User centric complex event processing based on service orien...

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28th Annual acm symposium on Applied Computing, SAC 2013

作者： Gao, Feng Bhiri, Sami Digital Enterprise Research Institute National University of Ireland Galway Galway Ireland

ISBN: (纸本)9781450316569

Current Complex Event Processing (CEP) systems require considerable technical efforts for event pattern definition and event stream implementation. In this paper, we present a service oriented framework that provides a user centric way to define complex event patterns and implement the patterns automatically. We extend the Business Event Modeling Notations (BEMN) to allow the business users to describe their complex events with graphical notations. Member event specifications in such event patterns refer to services that deliver them. We then transform the event pattern into a stream query, subscribe to relevant services and obtain event streams required. Finally, we evaluate the query over primitive event streams to obtain results as complex events. Copyright 2013 acm.

关键词： Information services

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SPAA'12 - proceedings of the 24th acm symposium on parallelism in algorithms and architectures

SPAA'12 - Proceedings of the 24th ACM Symposium on Paralleli...

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24th acm symposium on parallelism in algorithms and architectures, SPAA'12

ISBN: (纸本)9781450312134

the proceedings contain 40 papers. the topics discussed include: time vs. space trade-offs for rendezvous in trees;allowing each node to communicate only once in a distributed system: shared whiteboard models;optimal and competitive runtime bounds for continuous, local gathering of mobile robots;online multi-robot exploration of grid graphs with rectangular obstacles;in search of parallel dimensions;delegation and nesting in best-effort hardware transactional memory;design, verification and applications of a new read-write lock algorithm;a lock-free B+tree;brief announcement: the problem based benchmark suite;brief announcement: subgraph isomorphism on a multithreaded shared memory architecture;efficient cache oblivious algorithms for randomized divide-and-conquer on the multicore model;a scalable framework for heterogeneous GPU-based clusters;and faster and simpler width-independent parallel algorithms for positive semidefinite programming.

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On-the-fly variation tolerant mapping in crossbar nano-architectures

On-the-fly variation tolerant mapping in crossbar nano-archi...

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28th IEEE VLSI Test symposium, VTS10

作者： Tunc, Cihan Tahoori, Mehdi B. Electrical and Computer Engineering Northeastern University Boston MA 02115 United States Karlsruhe Institute of Technology Karlsruhe 76131 Germany

ISBN: (纸本)9781424466481

In hybrid nano-architectures, self-assembled nanoscale crossbars are fabricated on top of a reliable CMOS subsystem. Bottom-up self-assembly nanofabrication process, used in nano-architectures, yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. this is in addition to an increased defect density expected for self-assembled nanodevices. therefore, it is one of the major design challenges to tolerate variation and defects in emerging nano architectures. In this paper, we present an alternative approach for variation and defect tolerant mapping in which no application-independent test and characterization (defect and variation map) is required. the variation tolerant mapping is done on-the-fly which can ultimately be transformed into built-in self-mapping. Different mapping algorithms are presented and their efficiencies in terms of variation and defect tolerance as well as mapping time are compared. the experimental results show that the proposed heuristic mapping algorithm can achieve the same success rate with the exhaustive method in terms of meeting required timing constraints with orders of magnitude fewer reconfiguration retries. ©2010 IEEE.

关键词： CMOS integrated circuits

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SPAA'08 - proceedings of the 20th Annual symposium on parallelism in algorithms and architectures

SPAA'08 - Proceedings of the 20th Annual Symposium on Parall...

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20th acm symposium on parallelism in algorithms and architectures, SPAA'08

ISBN: (纸本)9781595939739

the proceedings contain 53 papers. the topics discussed include: a first insight into object-aware hardware transactional memory;safe open-nested transactions through ownership;leveraging non-blocking collective communication in high-performance applications;fractal communication in software data dependency graphs;many random walks are faster than one;improved distributed approximate matching;graph partitioning into isolated, high conductance clusters: theory, commutation and applications to preconditioning;automatic data partitioning in software transactional memories;checkpoints and continuations instead of nested transactions;adaptive transaction scheduling for transactional memory systems;operational analysis of processor speed scaling;and kicking the tires of software transactional memory: why the going gets tough.

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SPAA'07: proceedings of the Nineteenth Annual symposium on parallelism in algorithms and architectures

SPAA'07: Proceedings of the Nineteenth Annual Symposium on P...

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SPAA'07: 19th Annual symposium on parallelism in algorithms and architectures

ISBN: (纸本)159593667X

the proceedings contain 37 papers. the topics discussed include: on triangulation of simple networks;strong-diameter decompositions of minor free graphs;approximation algorithms for multiprocessor scheduling under uncertainty;scheduling DAGs on asynchronous processors;scheduling to minimize gaps and power consumption;cache-oblivious streaming B-trees;an experimental comparison of cache-oblivious and cache-conscious programs;scheduling threads for constructive cache sharing on CMPs;proximity-aware directory-based coherence for multi-core processor architectures;a parallel dynamic programming algorithm on a multi-core architecture;tight bounds for distributed selection;local MST computation with short advice;distributed approximation of capacitated dominating sets;packing to angles and sectors;and the notion of a timed register and its application to indulgent synchronization.

关键词： Computer programming

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SuperMatrix Out-of-Order Scheduling of Matrix Operations for SMP and Multi-Core architectures 07

SuperMatrix Out-of-Order Scheduling of Matrix Operations for...

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19th Annual symposium on parallelism in algorithms and architectures

作者： Chan, Ernie Quintana-Orti, Enrique S. Quintana-Orti, Gregorio van de Geijn, Robert Univ Texas Austin Dept Comp Sci Austin TX 78712 USA Univ Jaume 1 Dept Ingn & Ciencia Computad Castellon de La Plana Spain

ISBN: (纸本)9781595936677

We discuss the high-performance parallel implementation and execution of dense linear algebra matrix operations on SMP architectures;with an eye towards multi-core processors with many cores. We argue that traditional implementations, as those incorporated in LAPACK, cannot be easily modified to render high performance as well as scalability on these architectures. the solution we propose is to arrange the data structures and algorithms so that matrix blocks become the fundamental units of data;and operations on these blocks become the fundamental units of computation, resulting in algorithms-by-blocks as opposed to the snore traditional blocked algorithms. We show that this facilitates the adoption of techniques akin to dynamic scheduling and out-of-order execution usual in superscalar processors;which we name SuperMatrix Out-of-Order scheduling. Performance results on a 16 CPU Itanium2-based server are used to highlight opportunities and issues related to this new approach.

关键词： data affinity data-flow parallelism dense linear algebra libraries dynamic scheduling out-of-order execution

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Proximity-Aware Directory-based Coherence for Multi-core Processor architectures 07

Proximity-Aware Directory-based Coherence for Multi-core Pro...

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19th Annual symposium on parallelism in algorithms and architectures

作者： Brown, Jeffery A. Kumar, Rakesh Tullsen, Dean Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA

ISBN: (纸本)9781595936677

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. this is exacerbated by the fact that interconnection speeds are not scaling well with technology. this paper describes mechanisms to accelerate coherence for a multi-core architecture that has multiple private L2 caches and a scalable point-to-point interconnect between cores. these techniques exploit the differences in geometry between chip multiprocessors and traditional multiprocessor architectures. Directory-based protocols have been proposed as a scalable alternative to snoop-based protocols. In this paper, we discuss implementations of coherence for CMPs and propose and evaluate a novel directory-based coherence scheme to improve the performance of parallel programs on such processors. Proximity-aware coherence accelerates read and write misses by initiating cache-to-cache transfers from the spatially closest sharer. this has the dual benefit of eliminating unnecessary accesses to off-Chip memory, and minimizing the distance over which communicated data moves across the network. the proposed schemes result in speedups up to 74.9% for our workloads.

关键词： Chip Multiprocessors Coherence

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SPAA 2006: 18th Annual acm symposium on parallelism in algorithms and architectures

SPAA 2006: 18th Annual ACM Symposium on Parallelism in Algor...

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SPAA 2006: 18th Annual acm symposium on parallelism in algorithms and architectures

ISBN: (纸本)1595934529

the proceedings contain 43 papers. the topics discussed include: publish and perish: definition and analysis of an n-person publication impact game;exponential separation of quantum and classical online space complexity;minimizing the stretch when scheduling flows of biological requests;position paper and brief announcement: the FG programming environment - good and good for you;efficient parallel algorithms for dead sensor diagnosis and multiple access channels;on the communication complexity of randomized broadcasting in random-like graphs;strip packing with precedence constraints and strip packing with release times;on space-stretch trade-offs: lower bounds;a performance analysis of local synchronization;the cache complexity of multithreaded cache oblivious algorithms;and deterministic load balancing and dictionaries in the parallel disk model.

关键词： Computer architecture

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symposium on parallelism in algorithms and architectures, SPAA 2003: 15th Annual symposium on parallelism in algorithms and architectures

Symposium on Parallelism in Algorithms and Architectures, SP...

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4th acm Federated Computing Research Conference, FCRC 2003

the proceedings contain 7 papers from the symposium on parallelism in algorithms and architectures, SPAA 2003: 15th Annual symposium on parallelism in algorithms and architectures. the topics discussed include: a practical algorithm for constructing oblivious routing schemes;novel architectures for P2P applications: the continuous-discrete approach;quantifying instruction criticality for shared memory multiprocessors;relaxing the problem-size bound for out-of-core columnsort;the complexity of verifying memory coherence;a near optimal scheduler for switch-memory-switch routers;and on local algorithms for topology control and routing in ad hoc networks.

关键词： Computer science

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