检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

59 篇 会议

馆藏范围

59 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

41 篇 工学
- 37 篇 计算机科学与技术...
- 16 篇 软件工程
- 7 篇 电气工程
- 2 篇 电子科学与技术（可...
- 2 篇 信息与通信工程
- 1 篇 机械工程
- 1 篇 光学工程
- 1 篇 材料科学与工程（可...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 生物工程
- 1 篇 安全科学与工程
10 篇 理学
- 8 篇 数学
- 2 篇 物理学
- 2 篇 统计学（可授理学、...
- 1 篇 生物学
- 1 篇 系统科学
5 篇 管理学
- 4 篇 管理科学与工程(可...
- 2 篇 工商管理
- 1 篇 图书情报与档案管...

主题

5 篇 scheduling
4 篇 parallel archite...
4 篇 computer archite...
3 篇 reconfigurable a...
3 篇 delay
2 篇 computer science
2 篇 scalability
2 篇 registers
2 篇 asynchronous var...
2 篇 static analysis
2 篇 dependence graph
2 篇 multicore archit...
2 篇 costs
2 篇 computer program...
2 篇 high performance...
2 篇 program compiler...
2 篇 hardware
2 篇 field programmab...
2 篇 dynamic scheduli...
2 篇 design methodolo...

机构

2 篇 univ texas austi...
2 篇 ohio state univ ...
2 篇 univ calif berke...
1 篇 math. & computer...
1 篇 department of co...
1 篇 univ texas austi...
1 篇 univ politecn ca...
1 篇 ohio state univ ...
1 篇 lawrence livermo...
1 篇 brookhaven natio...
1 篇 tsinghua univ ct...
1 篇 tsinghua univ tn...
1 篇 lawrence livermo...
1 篇 federal universi...
1 篇 univ jaume 1 dep...
1 篇 pacific nw natl ...
1 篇 univ passau inst...
1 篇 hunan univ coll ...
1 篇 department of el...
1 篇 university of ch...

作者

2 篇 song shuaiwen le...
1 篇 wang qinggang
1 篇 nassi ike
1 篇 bellini riccardo
1 篇 chan ernie
1 篇 rülke s
1 篇 dehnavi maryam m...
1 篇 chen hang
1 篇 cotet costel emi...
1 篇 lee yunsup
1 篇 du jiayi
1 篇 pilato christian
1 篇 zhang minjia
1 篇 kaya kamer
1 篇 li kenli
1 篇 zheng long
1 篇 h. corporaal
1 篇 barker kevin
1 篇 mehta gayatri
1 篇 jin ruoming

语言

59 篇 英文

检索条件"任意字段=Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures"

共 59 条记录，以下是51-60 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Enhanced reusability for SoC-based HW/SW co-design

Enhanced reusability for SoC-based HW/SW co-design

引用

Joint Meeting of the 28th EUROMICRO Conference/EUROMICRO symposium on Digital System Design

作者： Boden, M Schneider, J Feske, K Rülke, S FhG IIS Erlangen Branch Lab DA Dresden D-01069 Dresden Germany

ISBN: (纸本)0769517919

this paper addresses design methods for SoC-based HW/SW systems using reconfigurable architectures. the emphasis is the development of a method to enhance the reusability of HW and SW in the co-design process using proven languages like ANSI-C and VHDL. We distinguish between three abstraction layers for design modules consisting of both HW and SW this approach benefits the reuse of HW sources as well as SW sources for different applications as well as on different devices. We utilize the reconfigurable SoC Atmel FPSLIC for experimental tests and obtain a significant reuse ratio.

关键词： Context Costs Design methodology Field programmable gate arrays Global Positioning System Mobile handsets Partitioning algorithms Reconfigurable architectures Reconfigurable logic Testing

来源：评论

学校读者我要写书评

暂无评论

Towards a specification technique for component-based measurement and control software for embedded systems

Towards a specification technique for component-based measur...

引用

Joint Meeting of the 28th EUROMICRO Conference/EUROMICRO symposium on Digital System Design

作者： Maydl, W Sick, B Grass, W Univ Passau Inst Comp Architectures D-94032 Passau Germany

ISBN: (纸本)0769517870

this article deals with one of the major problems in component-based software development: the derivation of properties of a component system from given properties of components and rules for their interaction. Whereas properties of components can be analyzed and described by a software engineer responsible for component construction, many properties of an overall component system cannot be guaranteed in advance due to the late composition of components, for example by application engineers working for third parties. In the area of measurement, signal processing, and control in embedded systems, components encapsulating signal processing algorithms or signal adaptation algorithms can be modeled by means of a hierarchy of dataflow languages: synchronous (SDF), boolean controlled (BDF), and dynamic (DDF) dataflow. If the application engineer responsible for component assembly restricts to the use of SDF components, the component system will be computationally analyzable. that is, it can be decided if it is deadlock-free, the required amount of memory can be determined, and a cyclic schedule of component instances can be computed. If the application engineer uses SDF and BDF components only, the component system will still be deterministic. the objective of this paper is to describe a novel concept of a component framework for the afore-mentioned application area which can automatically determine certain global properties of a component system during component assembly, whenever possible. the application engineer benefits from the integrated techniques without having detailed knowledge of the underlying theory.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

Statistical scalability analysis of communication operations in distributed applications 01

Statistical scalability analysis of communication operations...

引用

8th acm SIGPLAN symposium on the Principles and Practice of Parallel Computing

作者： Vetter, JS McCracken, MO Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781581133462

Current trends in high performance computing suggest that users will soon have widespread access to clusters of multiprocessors with hundreds, if not thousands, of processors. this unprecedented degree of parallelism will undoubtedly expose scalability limitations in existing applications, where scalability is the ability of a parallel algorithm on a parallel architecture to effectively utilize an increasing number of processors. Users will need precise and automated techniques for detecting the cause of limited scalability. this paper addresses this dilemma. First, we argue that users face numerous challenges in understanding application scalability: managing substantial amounts of experiment data, extracting useful trends from this data, and reconciling performance information with their application's design. Second, we propose a solution to automate this data analysis problem by applying fundamental statistical techniques to scalability experiment data. Finally, we evaluate our operational prototype on several applications, and show that statistical techniques offer an effective strategy for assessing application scalability. In particular, we find that non-parametric correlation of the number of tasks to the ratio of the time for communication operations to overall communication time provides a reliable measure for identifying communication operations that scale poorly.

关键词： Scalability Experimental data statistical techniques Consumers Communication Research Automated recording Parallel architectures Surgery Multiprocessor High Performance Computing Parallel algorithms

来源：评论

学校读者我要写书评

暂无评论

proceedings of the 1995 28th Annual International symposium on Microarchitecture

Proceedings of the 1995 28th Annual International Symposium ...

引用

proceedings of the 1995 28th Annual International symposium on Microarchitecture

the proceedings contains 37 papers. Topics discussed include performance of branch correlation schemes, instruction level parallelism compilation, computer memory systems, software pipelining, data flow and multithreading architectures, branch architecture analysis, software and hardware object code translation, data prefetching, multithreading and superscalar design studies.

关键词： Software engineering

来源：评论

学校读者我要写书评

暂无评论

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures

Dynamic rescheduling: a technique for object code compatibil...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： T.M. Conte S.W. Sathaye Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a general-purpose computing paradigm. Previous approaches include hardware and software techniques, both of which have drawbacks. Hardware techniques add to the complexity of the architecture, whereas software techniques require multiple executables. this paper presents a technique called dynamic rescheduling that applies software techniques dynamically, using intervention by the operating system. Results are presented to demonstrate the viability of the technique using the Illinois IMPACT compiler and the TINKER architectural framework.

关键词： VLIW Computer architecture Delay Hardware Operating systems Protection Dynamic scheduling Instruction sets

来源：评论

学校读者我要写书评

暂无评论

Partitioned register file for TTAs

Partitioned register file for TTAs

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： J. Janssen H. Corporaal Department of Electrical Engineering Delft University of Technnology Delft Netherlands

A practical implementation of high performance instruction level parallel architectures is constrained by the difficulty to build a large monolithic multi-ported register file (RF). A solution is to partition the RF into smaller RFs while keeping the total number of registers and ports equal. this paper applies RF partitioning to transport triggered architectures (TTAs); these architectures are of the VLIW type. One may expect that partitioning increases the number of executed cycles because it constrains the number of ports per RF. It is shown that these performance losses are small; e.g. partitioning an RF with 24 registers and four read and four write ports into four RFs with 6 registers and one read and one write port gives a performance loss of only 5.8%. Partitioned RFs consume less area than monolithic RFs with the same number of ports and registers. Experiments show that, if the area saved by partitioning is spent on extra registers, partitioning does, on average, not reduce the performance; it may even result in a small performance gain.

关键词： Radio frequency Registers Performance loss VLIW Vector processors Parallel architectures Performance gain Delay Energy consumption Hardware

来源：评论

学校读者我要写书评

暂无评论

Design of storage hierarchy in multithreaded architectures

Design of storage hierarchy in multithreaded architectures

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： L. Roh W.A. Najjar Math. & Computer Science Division Argonne National Laboratory Argonne IL USA Department of Computer Science Colorado State University Fort Collins CO USA

Multithreaded execution models attempt to combine some aspects of dataflow-like execution with von Neumann model execution. their main objective is to mask the latency of inter-processor communications and remote memory accesses in large scale multiprocessors. An important issue in the analysis and evaluation of multithreaded execution is the design and performance of the storage hierarchy. Because of the sequential execution of threads, the locality of access within an executing thread can be exploited using registers and cache. At the inter-thread level, however, the locality of accesses to memory and its effect on the cache is not yet well understood. A storage model which can exploit this locality is developed and evaluated. the results indicate there is a large amount of inter-thread locality that can be exploited and that we can get an efficient storage system by exploiting the characteristics of nonblocking threads.

关键词： Yarn Multithreading Computer science Delay Switches Costs Computer architecture Laboratories Large-scale systems Registers

来源：评论

学校读者我要写书评

暂无评论

28th ANNUAL symposium ON FOUNDATIONS OF COMPUTER SCIENCE.

28TH ANNUAL SYMPOSIUM ON FOUNDATIONS OF COMPUTER SCIENCE.

引用

28th Annual symposium on Foundations of Computer Science.

作者： Anon

the following topics are dealt with: algorithms;robots;automata;computation theory;parallel computation;graph theory;distributed architectures;and cryptography. the proceedings contains 32 papers.

ISBN: (纸本)0818608072

the following topics are dealt with: algorithms;robots;automata;computation theory;parallel computation;graph theory;distributed architectures;and cryptography. the proceedings contains 32 papers.

关键词： COMPUTER PROGRAMMING

来源：评论

学校读者我要写书评

暂无评论

PARALLEL algorithms AND architectures FOR RULE-BASED SYSTEMS.

PARALLEL ALGORITHMS AND ARCHITECTURES FOR RULE-BASED SYSTEMS...

引用

13th Annual International symposium on Computer Architecture - Conference proceedings.

作者： Gupta, Anoop Forgy, Charles Newell, Allen Wedig, Robert Carnegie-Mellon Univ Pittsburgh PA USA Carnegie-Mellon Univ Pittsburgh PA USA

ISBN: (纸本)081860719X

Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from parallelism is quite limited, less than 10-fold. the reasons for the small speedup are: (1) the small number of rules relevant to each change to data memory;(2) the large variation in the processing required by the relevant rules;and (3) the small number of changes made to data memory between synchronization steps. To obtain this limited factor of 10-fold speedup, it is necessary to exploit parallelism at a very fine granularity. It is suggested that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/s. this speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

关键词： Computer systems, Digital

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共6页 << < 1 2 3 4 5 6 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：