检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

49 篇 会议

馆藏范围

49 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

26 篇 工学
- 26 篇 计算机科学与技术...
- 16 篇 软件工程
- 3 篇 电气工程
- 3 篇 信息与通信工程
- 2 篇 电子科学与技术（可...
- 1 篇 光学工程
- 1 篇 材料科学与工程（可...
- 1 篇 动力工程及工程热...
- 1 篇 控制科学与工程
- 1 篇 生物工程
10 篇 理学
- 9 篇 数学
- 1 篇 物理学
- 1 篇 生物学
- 1 篇 统计学（可授理学、...
4 篇 管理学
- 4 篇 管理科学与工程(可...
- 3 篇 工商管理
- 1 篇 图书情报与档案管...
1 篇 经济学
- 1 篇 应用经济学

主题

6 篇 parallel archite...
6 篇 computer archite...
5 篇 hardware
3 篇 microcomputers
3 篇 scheduling
3 篇 dynamic scheduli...
3 篇 vliw
2 篇 parallel algorit...
2 篇 hard discs
2 篇 graphics process...
2 篇 asynchronous var...
2 篇 laboratories
2 篇 concurrent data ...
2 篇 processor schedu...
2 篇 dependence graph
2 篇 program processo...
2 篇 instruction sets
2 篇 pipelines
2 篇 graphics process...
2 篇 encoding

机构

2 篇 department of el...
2 篇 north carolina s...
2 篇 univ texas austi...
2 篇 univ calif berke...
1 篇 univ texas austi...
1 篇 hewlett packard ...
1 篇 universidade fed...
1 篇 samsung semicond...
1 篇 brookhaven natio...
1 篇 dept. of compute...
1 篇 university lille...
1 篇 université nice ...
1 篇 univ jaume 1 dep...
1 篇 university of ch...
1 篇 iit dept comp sc...
1 篇 uc santa cruz sa...
1 篇 univ chicago dep...
1 篇 tech univ darmst...
1 篇 huazhong univ sc...
1 篇 universidade fed...

作者

2 篇 s.w. sathaye
2 篇 s. banerjia
2 篇 banerjia sanjeev
2 篇 conte thomas m.
2 篇 t.m. conte
2 篇 sathaye sumedh w...
1 篇 raicu ioan
1 篇 chan ernie
1 篇 lee yunsup
1 篇 park chanik
1 篇 luciano agostini
1 篇 marcelo porto
1 篇 krste asanović
1 篇 kang yangwook
1 篇 gustavo smaniott...
1 篇 andrade guilherm...
1 篇 menezes kishore ...
1 篇 seemaier daniel
1 篇 crotty andrew
1 篇 huang ping

语言

49 篇 英文

检索条件"任意字段=Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and Architectures"

共 49 条记录，以下是21-30 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Enabling Cost-effective Data Processing with Smart SSD

Enabling Cost-effective Data Processing with Smart SSD

引用

29th IEEE symposium on Massive Storage Systems and Technologies (MSST) - Research Track

作者： Kang, Yangwook Kee, Yang-suk Miller, Ethan L. Park, Chanik UC Santa Cruz Santa Cruz CA 95064 USA Samsung Semicond Inc Syst Architecture Lab San Jose CA USA Samsung Elect Suwon South Korea

ISBN: (纸本)9781479902170;9781479902187

this paper explores the benefits and limitations of in-storage processing on current Solid-State Disk (SSD) architectures. While disk-based in-storage processing has not been widely adopted, due to the characteristics of hard disks, modern SSDs provide high performance on concurrent random writes, and have powerful processors, memory, and multiple I/O channels to flash memory, enabling in-storage processing with almost no hardware changes. In addition, offloading I/O tasks allows a host system to fully utilize devices' internal parallelism without knowing the details of their hardware configurations. To leverage the enhanced data processing capabilities of modern SSDs, we introduce the Smart SSD model, which pairs in-device processing with a powerful host system capable of handling data-oriented tasks without modifying operating system code. By isolating the data traffic within the device, this model promises low energy consumption, high parallelism, low host memory footprint and better performance. To demonstrate these capabilities, we constructed a prototype implementing this model on a real SATA-based SSD. Our system uses an object-based protocol for low-level communication with the host, and extends the Hadoop MapReduce framework to support a Smart SSD. Our experiments show that total energy consumption is reduced by 50% due to the low-power processing inside a Smart SSD. Moreover, a system with a Smart SSD can outperform host-side processing by a factor of two or three by efficiently utilizing internal parallelism when applications have light trafic to the device DRAM under the current architecture.

关键词： DRAM chips energy consumption flash memories hard discs operating systems (computers) parallel architectures

来源：评论

学校读者我要写书评

暂无评论

Increasing the instruction fetch rate via block-structured instruction set architectures

Increasing the instruction fetch rate via block-structured i...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Hao, Eric Chang, Po-Yung Evers, Marius Patt, Yale N. Univ of Michigan Ann Arbor United States

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rate. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the instruction fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.

关键词： Microcomputers

来源：评论

学校读者我要写书评

暂无评论

Convergence and Scalarization for Data-Parallel architectures

Convergence and Scalarization for Data-Parallel Architecture...

引用

11th IEEE/acm International symposium on Code Generation and Optimization (CGO)

作者： Lee, Yunsup Krashinsky, Ronny Grover, Vinod Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781467355254;9781467355247

Modern throughput processors such as GPUs achieve high performance and efficiency by exploiting data parallelism in application kernels expressed as threaded code. One draw-back of this approach compared to conventional vector architectures is redundant execution of instructions that are common across multiple threads, resulting in energy inefficiency due to excess instruction dispatch, register file accesses, and memory operations. this paper proposes to alleviate these overheads while retaining the threaded programming model by automatically detecting the scalar operations and factoring them out of the parallel code. We have developed a scalarizing compiler that employs convergence and variance analyses to statically identify values and instructions that are invariant across multiple threads. Our compiler algorithms are effective at identifying convergent execution even in programs with arbitrary control flow, identifying two-thirds of the opportunity captured by a dynamic oracle. the compile-time analysis leads to a reduction in instructions dispatched by 29%, register file reads and writes by 31%, memory address counts by 47%, and data access counts by 38%.

关键词： CUDA GPU Scalarization

来源：评论

学校读者我要写书评

暂无评论

proceedings - 29th International symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2017

Proceedings - 29th International Symposium on Computer Archi...

引用

29th International symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2017

ISBN: (纸本)9781538648193

the proceedings contain 19 papers. the topics discussed include: energy consumption improvement of shared-cache multicore clusters based on explicit simultaneous multithreading;performance and energy analysis of OpenMP runtime systems with dense linear algebra algorithms;a case study of performance optimization in a heterogeneous environment;tuning up TVD HOPMOC method on Intel MIC Xeon Phi architectures with Intel parallel studio tools;comparing performance of C compilers optimizations on different multicore architectures;HPSM: a programming framework for multi-CPU and multi-GPU systems;assessing sparse triangular linear system solvers on GPUs;automatic partitioning of stencil computations on heterogeneous systems;strategies to improve the performance of a geophysics model for different Manycore systems;parallel algorithm for dynamic community detection;efficient in-situ quantum computing simulation of Shor's and Grover's algorithms;a parallel algorithm for minimum spanning tree on GPU;acceleration of cellular automata through parallel computing with OpenCL;a dataflow implementation of region growing method for cracks segmentation;automatic scan parallelization in OpenMP;impact of version management for transactional memories on phase-change memories;efficient Pathfinding co-processors for FPGAs;and a communication protocol for fog computing based on network coding applied to wireless sensors.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Enabling Extremely Fine-grained parallelism via Scalable Concurrent Queues on Modern Many-core architectures 29

Enabling Extremely Fine-grained Parallelism via Scalable Con...

引用

29th International symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Nookala, Poornima Dinda, Peter Hale, Kyle C. Chard, Kyle Raicu, Ioan IIT Dept Comp Sci Chicago IL 60616 USA Northwestern Univ Dept Comp Sci Evanston IL USA Univ Chicago Dept Comp Sci Chicago IL 60637 USA

ISBN: (纸本)9781665458382

Enabling efficient fine-grained task parallelism is a significant challenge for hardware platforms with increasingly many cores. Existing techniques do not scale to hundreds of threads due to the high cost of synchronization in concurrent data structures. To overcome these limitations we present XQueue, a novel lock-less concurrent queuing system with relaxed ordering semantics that is geared towards realizing scalability up to hundreds of concurrent threads. We demonstrate the scalability of XQueue using microbenchmarks and show that XQueue can deliver concurrent operations with latencies as low as 110 cycles at scales of up to 192 cores (up to 6900x improvement compared to traditional synchronization mechanisms) across our diverse hardware, including x86, ARM, and Power9. the reduced latency allows XQueue to provide orders of magnitude (3300x) better throughput that existing techniques. To evaluate the real-world benefits of XQueue, we integrated XQueue with LLVM OpenMP and evaluated five unmodified benchmarks from the Barcelona OpenMP Task Suite (BOTS) as well as a graph traversal benchmark from the GAP benchmark suite. We compared the XQueue-enabled LLVM OpenMP implementation with the native LLVM and GNU OpenMP versions. Using fine-grained task workloads, XQueue can deliver 4x to 6x speedup compared to native GNU OpenMP and LLVM OpenMP in many cases, with speedups as high as 116x in some cases.

关键词： concurrent data structures fine-grained parallelism lock-free lock-less queues parallel runtime tasks

来源：评论

学校读者我要写书评

暂无评论

Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN architectures 29

Cache Telepathy: Leveraging Shared Resource Attacks to Learn...

引用

29th USENIX Security symposium

作者： Yan, Mengjia Fletcher, Christopher W. Torrellas, Josep Univ Illinois Champaign IL 61820 USA

ISBN: (纸本)9781939133175

Deep Neural Networks (DNNs) are fast becoming ubiquitous for their ability to attain good accuracy in various machine learning tasks. A DNN's architecture (i.e., its hyperparameters) broadly determines the DNN's accuracy and performance, and is often confidential. Attacking a DNN in the cloud to obtain its architecture can potentially provide major commercial value. Further, attaining a DNN's architecture facilitates other existing DNN attacks. this paper presents Cache Telepathy: an efficient mechanism to help obtain a DNN's architecture using the cache side channel. the attack is based on the insight that DNN inference relies heavily on tiled GEMM (Generalized Matrix Multiply), and that DNN architecture parameters determine the number of GEMM calls and the dimensions of the matrices used in the GEMM functions. Such information can be leaked through the cache side channel. this paper uses Prime+Probe and Flush+Reload to attack the VGG and ResNet DNNs running OpenBLAS and Intel MKL libraries. Our attack is effective in helping obtain the DNN architectures by very substantially reducing the search space of target DNN architectures. For example, when attacking the OpenBLAS library, for the different layers in VGG-16, it reduces the search space from more than 5.4 x 10(12) architectures to just 16;for the different modules in ResNet-50, it reduces the search space from more than 6 x 10(46) architectures to only 512.

关键词： Deep neural networks

来源：评论

学校读者我要写书评

暂无评论

HiDP: A Hierarchical Data Parallel Language

HiDP: A Hierarchical Data Parallel Language

引用

11th IEEE/acm International symposium on Code Generation and Optimization (CGO)

作者： Zhang, Yongpeng Mueller, Frank N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781467355254;9781467355247

Problem domains are commonly decomposed hierarchically to fully utilize parallel resources in modern microprocessors. Such decompositions can be provided as library routines, written by experienced experts, for general algorithmic patterns. But such APIs tend to be constrained to certain architectures or data sizes. Integrating them with application code is often an unnecessarily daunting task, especially when these routines need to be closely coupled with user code to achieve better performance. this paper contributes HiDP, a high-level hierarchical data parallel language. the purpose of HiDP is to improve the coding productivity of integrating hierarchical data parallelism without significant loss of performance. HiDP is a source-to-source compiler that converts a very concise data parallel language into CUDA C++ source code. Internally, it performs necessary analysis to compose user code with efficient and architecture-aware code snippets. this paper discusses various aspects of HiDP systematically: the language, the compiler and the run-time system with built-in tuning capabilities. they enable HiDP users to express algorithms in less code than low-level SDKs require for native platforms. HiDP also exposes abundant computing resources of modern parallel architectures. Improved coding productivity tends to come with a sacrifice in performance. Yet, experimental results show that the generated code delivers performance very close to handcrafted native GPU code.

关键词： C++ language application program interfaces graphics processing units microprocessor chips parallel architectures parallel languages program compilers source coding

来源：评论

学校读者我要写书评

暂无评论

Efficient dynamic scheduling of heterogeneous applications in hybrid architectures 14

Efficient dynamic scheduling of heterogeneous applications i...

引用

29th Annual acm symposium on Applied Computing, SAC 2014

作者： Andrade, Guilherme Ramos, Gabriel Madeira, Daniel Sachetto, Rafael Clua, Esteban Ferreira, Renato Rocha, Leonardo Universidade Federal de São João Del Rey Computer Science São João Del Rei Brazil Universidade Federal de Minas Gerais Computer Science Belo Horizonte Brazil Universidade Federal Fluminense Computer Science Niterói Brazil

ISBN: (纸本)9781450324694

the emergence of different applications that deal with growing amounts of data at reasonable times, has stimulated the development of new computing architectures consisting of different processing units (PU). Runtime environments have been proposed in order to exploit these resource as much as possible by offering a variety of methods for dynamically scheduling tasks on different PUs. these schedulers determine which PU is better suited for executing each task, based upon a set of task parameters such as the amount of data, computation requirements, etc. Although large number of applications are heterogeneous, composed of tasks with different characteristics, the current techniques focus on these characteristics as isolated features leading to inefficient executions in several situations. In this work we present two new scheduling strategies, combining different existing strategies, that leads to more efficient executions in different scenarios. Our results show that our approach can be up to 20% more efficient than current techniques. Copyright 2014 acm.

关键词： Parallel algorithms

来源：评论

学校读者我要写书评

暂无评论

Instruction fetch mechanisms for VLIW architectures with compressed encodings

Instruction fetch mechanisms for VLIW architectures with com...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Conte, thomas M. Banerjia, Sanjeev Larin, Sergei Y. Menezes, Kishore N. Sathaye, Sumedh W. North Carolina State Univ Raleigh United States

VLIW architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. this report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs. A compressed instruction encoding for VLIWs is defined, and a classification scheme for i-fetch hardware for such an encoding is introduced. Several interesting cache and i-fetch organizations are described and evaluated through trace-driven simulations. A new i-fetch mechanism using a silo cache is found to have the best performance.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Custom-fit processors: Letting applications define architectures

Custom-fit processors: Letting applications define architect...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Fisher, Joseph A. Faraboschi, Paolo Desoli, Giuseppe Hewlett-Packard Lab Cambridge Cambridge United States

In this paper we report on a system which automatically designs realistic VLIW architectures highly optimized for one given application (the input for this system), while running all other code correctly. the system uses a product-quality compiler that generates very aggressive VLIW code. We retarget the compiler until we have found a VLIW architecture idealized for the application on the basis of performance, a cost function and a hardware budget. We show that we can automatically select architectures that achieve large speedups on color and image processing codes. Specialization is shown to be very valuable: the differences between architectural choices, even among reasonable-seeming architectures having similar costs, can be very great, often a factor of 5 (and sometimes much more). We show also that specialization is also very dangerous. A reasonable choice of architecture to fit one algorithm can be a very poor choice for another, even in the same domain. there is sometimes an architecture, near in cost and performance to the best, that does much better on a second algorithm.

关键词： Microcomputers

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共5页 << < 1 2 3 4 5 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：