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proceedings - 29th International symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017

Proceedings - 29th International Symposium on Computer Archi...

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29th International symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017

ISBN: (纸本)9781509012336

the proceedings contain 23 papers. the topics discussed include: extending OmpSs for OpenCL kernel co-execution in heterogeneous systems;data coherence analysis and optimization for heterogeneous computing;exploring heterogeneous mobile architectures with a high-level programming model;scalability of CPU and GPU solutions of the prime elliptic curve discrete logarithm problem;overcoming memory-capacity constraints in the use of ILUPACK on graphics processors;exploiting data compression to mitigate aging in GPU register files;SEDEA: a sensible approach to account DRAM energy in multicore systems;a user-level scheduling framework for BoT applications on private clouds;GC-CR: a decentralized garbage collector component for checkpointing in clouds;towards a deterministic fine-grained task ordering using multi-versioned memory;FGSCM: a fine-grained approach to transactional lock elision;a machine learning approach for performance prediction and scheduling on heterogeneous CPUs;object placement for high bandwidth memory augmented with high capacity memory;accelerating graph analytics on CPU-FPGA heterogeneous platform;online multimedia similarity search with response time-aware parallelism and task granularity auto-tuning;a publish/subscribe system using causal broadcast over dynamically built spanning trees;global snapshot of a distributed system running on virtual machines;and resource-management study in HPC runtime-stacking context.

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the future of accelerator programming: Abstraction, performance or can we have both? 14

The future of accelerator programming: Abstraction, performa...

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29th Annual acm symposium on Applied Computing, SAC 2014

作者： Rocki, Kamil Burtscher, Martin Suda, Reiji IBM Research 650 Harry Road San Jose CA 95120 United States University of Tokyo Department of Computer Science 7-3-1 Hongo Bunkyo-ku Tokyo Japan Texas State University Department of Computer Science San Marcos TX 78666 United States

ISBN: (纸本)9781450324694

In a perfect world, code would only be written once and would run on different devices with high efficiency. To a degree, that used to be the case in the era of frequency scaling on a single core. However, due to power limitations, parallel programming has become necessary to obtain performance gains. But parallel architectures differ substantially from each other, often require specialized knowledge to exploit them, and typically necessitate reimplementation and fine tuning of programs. these slow tasks frequently result in situations where most of the time is spent reimplementing old rather than writing new code. the goal of our research is to find programming techniques that increase productivity, maintain high performance, and provide abstraction to free the programmer from these unnecessary and time-consuming tasks. However, such techniques usually come at the cost of substantial performance degradation. this paper investigates current approaches to portable accelerator programming, seeking to answer whether they make it possible to combine high efficiency with sufficient algorithm abstraction. It discusses OpenCL as a potential solution and presents three approaches of writing portable code: GPU-centric, CPU-centric, and combined. By applying the three approaches to a real-world program, we show that it is at least sometimes possible to run exactly the same code on many different devices with minimal performance degradation using parameterization. the main contributions of this paper are an extensive review of the current state-of-the-art and our original approach of addressing the stated problem with the copious-parallelism technique. Copyright 2014 acm.

关键词： Parallel architectures

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proceedings - IEEE International symposium on Rapid System Prototyping, RSP

Proceedings - IEEE International Symposium on Rapid System P...

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29th International symposium on Rapid System Prototyping, RSP 2018

ISBN: (纸本)9781538675571

the proceedings contain 16 papers. the topics discussed include: synthesis of full hardware implementation of RTOS-based systems;estimating the impact of architectural and software design choices on dynamic allocation of heterogeneous memories;constraint specification language (CSL) use in the test program generator;rapid prototyping of parameterized rotated and cyclic Q delayed constellations demapper;assessment of a beaglebone black high sampling rate digital waveform generator;semantics-directed prototyping of hardware runtime monitors;prototyping energy harvesting powered systems with nonvolatile processor;rapid prototyping of embedded vision systems: embedding computer vision applications into low-power heterogeneous architectures;and ambient intelligence for the internet of things through context-awareness.

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A Novel I/O Scheduler for SSD with Improved Performance and Lifetime

A Novel I/O Scheduler for SSD with Improved Performance and ...

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29th IEEE symposium on Massive Storage Systems and Technologies (MSST) - Research Track

作者： Wang, Hua Huang, Ping He, Shuang Zhou, Ke Li, Chunhua He, Xubin Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan Peoples R China Virginia Commonwealth Univ Dept Elect & Comp Engn Richmond VA USA

ISBN: (纸本)9781479902170;9781479902187

this paper presents a novel block I/O scheduler specifically for SSDs. the scheduler leverages the internal rich parallelism resulting from SSD's highly parallelized architecture. It speculatively divides the entire SSD space into different subregions and dispatches requests into those subregions in a round-robin fashion at the Linux kernel block layer. In the meanwhile, to reduce the severe read-write interference problem associated with SSDs, the scheduler only dispatches a batch of unidirectional requests to the disk driver for each subregion's scheduling opportunity. Furthermore, to take advantage of SSD'S better sequential performance over random patterns, the scheduler sorts the pending requests while they are awaiting in the dispatching queues as those HDD-oriented schedulers do. the experimental results with a variety of workloads have demonstrated that the new I/O scheduler not only improves the user-perceived performance, but also enhances the underlying SSD's lifetime via reducing the block erase operations during the running processes.

关键词： Linux disc drives hard discs parallel architectures processor scheduling queueing theory sorting

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PARALLEL algorithms AND architectures FOR RULE-BASED SYSTEMS.

PARALLEL ALGORITHMS AND ARCHITECTURES FOR RULE-BASED SYSTEMS...

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13th Annual International symposium on Computer Architecture - Conference proceedings.

作者： Gupta, Anoop Forgy, Charles Newell, Allen Wedig, Robert Carnegie-Mellon Univ Pittsburgh PA USA Carnegie-Mellon Univ Pittsburgh PA USA

ISBN: (纸本)081860719X

Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from parallelism is quite limited, less than 10-fold. the reasons for the small speedup are: (1) the small number of rules relevant to each change to data memory;(2) the large variation in the processing required by the relevant rules;and (3) the small number of changes made to data memory between synchronization steps. To obtain this limited factor of 10-fold speedup, it is necessary to exploit parallelism at a very fine granularity. It is suggested that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/s. this speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

关键词： Computer systems, Digital

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Statistical scalability analysis of communication operations in distributed applications 01

Statistical scalability analysis of communication operations...

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8th acm SIGPLAN symposium on the Principles and Practice of Parallel Computing

作者： Vetter, JS McCracken, MO Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94551 USA

ISBN: (纸本)9781581133462

Current trends in high performance computing suggest that users will soon have widespread access to clusters of multiprocessors with hundreds, if not thousands, of processors. this unprecedented degree of parallelism will undoubtedly expose scalability limitations in existing applications, where scalability is the ability of a parallel algorithm on a parallel architecture to effectively utilize an increasing number of processors. Users will need precise and automated techniques for detecting the cause of limited scalability. this paper addresses this dilemma. First, we argue that users face numerous challenges in understanding application scalability: managing substantial amounts of experiment data, extracting useful trends from this data, and reconciling performance information with their application's design. Second, we propose a solution to automate this data analysis problem by applying fundamental statistical techniques to scalability experiment data. Finally, we evaluate our operational prototype on several applications, and show that statistical techniques offer an effective strategy for assessing application scalability. In particular, we find that non-parametric correlation of the number of tasks to the ratio of the time for communication operations to overall communication time provides a reliable measure for identifying communication operations that scale poorly.

关键词： Scalability Experimental data statistical techniques Consumers Communication Research Automated recording Parallel architectures Surgery Multiprocessor High Performance Computing Parallel algorithms

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ACTRESS: Domain-specific modeling of self-adaptive software architectures 14

ACTRESS: Domain-specific modeling of self-adaptive software ...

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29th Annual acm symposium on Applied Computing, SAC 2014

作者： Křikava, Filip Collet, Philippe France, Robert B. University Lille 1 LIFL Inria Lille Nord Europe France Université Nice I3S CNRS UMR 7271 Sophia Antipolis France Colorado State University CS Department Fort Collins United States

ISBN: (纸本)9781450324694

A common approach for engineering self-adaptive software systems is to use Feedback Control Loops (FCLs). Advances have led to more explicit and safer design of some control architectures, however, there is a need for more integrated and systematic approaches that support end-to-end integration of FCLs into software systems. In this paper, we propose a tooled approach that enables researchers and engineers to design and integrate adaptation mechanisms into software systems through FCLs. It consists of a domain-specific modeling language that raises the level of abstraction on which FCLs are defined, making them amenable to automated analysis and implementation code synthesis. the language supports composition, distribution and reflection, thereby enabling coordination and composition of multiple distributed FCLs. Its use is facilitated by a modeling environment, ACTRESS, that provides support for modeling, verification and complete code generation. We report on its application to a concrete adaptation case study and also discuss resulting properties. Copyright 2014 acm.

关键词： Adaptive control systems

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Persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures

Persistent rescheduled-page cache for low overhead object co...

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proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Conte, thomas M. Sathaye, Sumedh W. Banerjia, Sanjeev North Carolina State Univ Raleigh United States

Object-code compatibility between processor generations is an open issue for VLIW architectures. A potential solution is a technique termed dynamic rescheduling, which performs run-time software rescheduling at the first-time page faults. the time required for rescheduling the pages constitutes a large portion of the overhead of this method. A disk caching scheme that uses a persistent rescheduled-page cache (PRC) is presented. the scheme reduces the overhead associated with dynamic rescheduling by saving rescheduled pages on disk, across program executions. Operating system support is required for dynamic rescheduling and management of the PRC. the implementation details for the PRC are discussed. Results of simulations used to gauge the effectiveness of PRC indicate that (1) the PRC is effective in reducing the overhead of dynamic rescheduling, and (2) due to different overhead requirements of programs, a split PRC organization performs better than a unified PRC. the unified PRC was studied for two different page replacement policies: LRU and overhead-based replacement. It was found that with LRU replacement, all the programs consistently perform better with increasing PRC sizes, but the high-overhead programs take a consistent performance hit compared to the low-overhead programs. With overhead-based replacement, the performance of high-overhead programs improves substantially, while the low-overhead programs perform only slightly worse than in the case of the LRU replacement.

关键词： Microcomputers

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Rapid Prototyping of Embedded Vision Systems: Embedding Computer Vision Applications into Low-Power Heterogeneous architectures 29

Rapid Prototyping of Embedded Vision Systems: Embedding Comp...

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29th International symposium on Rapid System Prototyping, RSP 2018

作者： Aldegheri, Stefano Bombieri, Nicola Dept. of Computer Science University of Verona Italy

ISBN: (纸本)9781538675571

Embedded vision is a disruptive new technology in the vision industry. It is a revolutionary concept with far reaching implications, and it is opening up new applications and shaping the future of entire industries. It is applied in self-driving cars, autonomous vehicles in agriculture, digital dermascopes that help specialists make more accurate diagnoses, among many other unique and cutting-edge applications. the design of such systems gives rise to new challenges for embedded Software developers. Embedded vision applications are characterized by stringent performance constraints to guarantee real-time behaviours and, at the same time, energy constraints to save battery on the mobile platforms. In this paper, we address such challenges by proposing an overall view of the problem and by analysing current solutions. We present our last results on embedded vision design automation over two main aspects: the adoption of the model-based paradigm for the embedded vision rapid prototyping, and the application of heterogeneous programming languages to improve the system performance. the paper presents our recent results on the design of a localization and mapping application combined with image recognition based on deep learning optimized for an NVIDIA Jetson TX2. © 2018 IEEE.

关键词： Graphics processing unit

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Instruction fetch mechanisms for VLIW architectures with compressed encodings 29

Instruction fetch mechanisms for VLIW architectures with com...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： T.M. Conte S. Banerjia S.Y. Larin K.N. Menezes S.W. Sathaye Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

ISBN: (纸本)9780818676413

VLIW architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. this report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs. A compressed instruction encoding for VLIWs is defined and a classification scheme for i-fetch hardware for such an encoding is introduced. Several interesting cache and i-fetch organizations are described and evaluated through trace-driven simulations. A new i-fetch mechanism using a silo cache is found to have the best performance.

关键词： VLIW Encoding Scheduling Computer architecture Bandwidth Pipelines Hardware Testing Clocks Heuristic algorithms

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