检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

49 篇 会议

馆藏范围

49 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

26 篇 工学
- 26 篇 计算机科学与技术...
- 16 篇 软件工程
- 3 篇 电气工程
- 3 篇 信息与通信工程
- 2 篇 电子科学与技术（可...
- 1 篇 光学工程
- 1 篇 材料科学与工程（可...
- 1 篇 动力工程及工程热...
- 1 篇 控制科学与工程
- 1 篇 生物工程
10 篇 理学
- 9 篇 数学
- 1 篇 物理学
- 1 篇 生物学
- 1 篇 统计学（可授理学、...
4 篇 管理学
- 4 篇 管理科学与工程(可...
- 3 篇 工商管理
- 1 篇 图书情报与档案管...
1 篇 经济学
- 1 篇 应用经济学

主题

6 篇 parallel archite...
6 篇 computer archite...
5 篇 hardware
3 篇 microcomputers
3 篇 scheduling
3 篇 dynamic scheduli...
3 篇 vliw
2 篇 parallel algorit...
2 篇 hard discs
2 篇 graphics process...
2 篇 asynchronous var...
2 篇 laboratories
2 篇 concurrent data ...
2 篇 processor schedu...
2 篇 dependence graph
2 篇 program processo...
2 篇 instruction sets
2 篇 pipelines
2 篇 graphics process...
2 篇 encoding

机构

2 篇 department of el...
2 篇 north carolina s...
2 篇 univ texas austi...
2 篇 univ calif berke...
1 篇 univ texas austi...
1 篇 hewlett packard ...
1 篇 universidade fed...
1 篇 samsung semicond...
1 篇 brookhaven natio...
1 篇 dept. of compute...
1 篇 university lille...
1 篇 université nice ...
1 篇 univ jaume 1 dep...
1 篇 university of ch...
1 篇 iit dept comp sc...
1 篇 uc santa cruz sa...
1 篇 univ chicago dep...
1 篇 tech univ darmst...
1 篇 huazhong univ sc...
1 篇 universidade fed...

作者

2 篇 s.w. sathaye
2 篇 s. banerjia
2 篇 banerjia sanjeev
2 篇 conte thomas m.
2 篇 t.m. conte
2 篇 sathaye sumedh w...
1 篇 raicu ioan
1 篇 chan ernie
1 篇 lee yunsup
1 篇 park chanik
1 篇 luciano agostini
1 篇 marcelo porto
1 篇 krste asanović
1 篇 kang yangwook
1 篇 gustavo smaniott...
1 篇 andrade guilherm...
1 篇 menezes kishore ...
1 篇 seemaier daniel
1 篇 crotty andrew
1 篇 huang ping

语言

49 篇 英文

检索条件"任意字段=Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and Architectures"

共 49 条记录，以下是41-50 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Increasing the instruction fetch rate via block-structured instruction set architectures

Increasing the instruction fetch rate via block-structured i...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Hao, Eric Chang, Po-Yung Evers, Marius Patt, Yale N. Univ of Michigan Ann Arbor United States

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rate. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the instruction fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.

关键词： Microcomputers

来源：评论

学校读者我要写书评

暂无评论

Instruction fetch mechanisms for VLIW architectures with compressed encodings

Instruction fetch mechanisms for VLIW architectures with com...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Conte, thomas M. Banerjia, Sanjeev Larin, Sergei Y. Menezes, Kishore N. Sathaye, Sumedh W. North Carolina State Univ Raleigh United States

VLIW architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. this report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs. A compressed instruction encoding for VLIWs is defined, and a classification scheme for i-fetch hardware for such an encoding is introduced. Several interesting cache and i-fetch organizations are described and evaluated through trace-driven simulations. A new i-fetch mechanism using a silo cache is found to have the best performance.

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Custom-fit processors: Letting applications define architectures

Custom-fit processors: Letting applications define architect...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Fisher, Joseph A. Faraboschi, Paolo Desoli, Giuseppe Hewlett-Packard Lab Cambridge Cambridge United States

In this paper we report on a system which automatically designs realistic VLIW architectures highly optimized for one given application (the input for this system), while running all other code correctly. the system uses a product-quality compiler that generates very aggressive VLIW code. We retarget the compiler until we have found a VLIW architecture idealized for the application on the basis of performance, a cost function and a hardware budget. We show that we can automatically select architectures that achieve large speedups on color and image processing codes. Specialization is shown to be very valuable: the differences between architectural choices, even among reasonable-seeming architectures having similar costs, can be very great, often a factor of 5 (and sometimes much more). We show also that specialization is also very dangerous. A reasonable choice of architecture to fit one algorithm can be a very poor choice for another, even in the same domain. there is sometimes an architecture, near in cost and performance to the best, that does much better on a second algorithm.

关键词： Microcomputers

来源：评论

学校读者我要写书评

暂无评论

Persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures

Persistent rescheduled-page cache for low overhead object co...

引用

proceedings of the 1996 29th Annual IEEE/acm International symposium on Microarchitecture, MICRO-29

作者： Conte, thomas M. Sathaye, Sumedh W. Banerjia, Sanjeev North Carolina State Univ Raleigh United States

Object-code compatibility between processor generations is an open issue for VLIW architectures. A potential solution is a technique termed dynamic rescheduling, which performs run-time software rescheduling at the first-time page faults. the time required for rescheduling the pages constitutes a large portion of the overhead of this method. A disk caching scheme that uses a persistent rescheduled-page cache (PRC) is presented. the scheme reduces the overhead associated with dynamic rescheduling by saving rescheduled pages on disk, across program executions. Operating system support is required for dynamic rescheduling and management of the PRC. the implementation details for the PRC are discussed. Results of simulations used to gauge the effectiveness of PRC indicate that (1) the PRC is effective in reducing the overhead of dynamic rescheduling, and (2) due to different overhead requirements of programs, a split PRC organization performs better than a unified PRC. the unified PRC was studied for two different page replacement policies: LRU and overhead-based replacement. It was found that with LRU replacement, all the programs consistently perform better with increasing PRC sizes, but the high-overhead programs take a consistent performance hit compared to the low-overhead programs. With overhead-based replacement, the performance of high-overhead programs improves substantially, while the low-overhead programs perform only slightly worse than in the case of the LRU replacement.

关键词： Microcomputers

来源：评论

学校读者我要写书评

暂无评论

Instruction fetch mechanisms for VLIW architectures with compressed encodings 29

Instruction fetch mechanisms for VLIW architectures with com...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： T.M. Conte S. Banerjia S.Y. Larin K.N. Menezes S.W. Sathaye Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

ISBN: (纸本)9780818676413

VLIW architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. this report uses the TINKER experimental testbed to examine instruction fetch and instruction cache mechanisms for VLIWs. A compressed instruction encoding for VLIWs is defined and a classification scheme for i-fetch hardware for such an encoding is introduced. Several interesting cache and i-fetch organizations are described and evaluated through trace-driven simulations. A new i-fetch mechanism using a silo cache is found to have the best performance.

关键词： VLIW Encoding Scheduling Computer architecture Bandwidth Pipelines Hardware Testing Clocks Heuristic algorithms

来源：评论

学校读者我要写书评

暂无评论

Increasing the instruction fetch rate via block-structured instruction set architectures 29

Increasing the instruction fetch rate via block-structured i...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： E. Hao Po-Yung Chang M. Evers Y.N. Patt Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818676413

To exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance potential of such processors. Block-structured ISAs provide an effective means of increasing the instruction fetch rare. We define an optimization, called block enlargement, that can be applied to a block-structured ISA to increase the instruction fetch rate of a processor that implements that ISA. We have constructed a compiler that generates block-structured ISA code, and a simulator that models the execution of that code on a block-structured ISA processor. We show that for the SPECint95 benchmarks, the block-structured ISA processor executing enlarged atomic blocks outperforms a conventional ISA processor by 12% while using simpler microarchitectural mechanisms to support wide-issue and dynamic scheduling.

关键词： Instruction sets Computer architecture Parallel processing Sun Laboratories Microarchitecture Dynamic scheduling Pipelines Program processors Hardware

来源：评论

学校读者我要写书评

暂无评论

Custom-fit processors: letting applications define architectures 29

Custom-fit processors: letting applications define architect...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： J.A. Fisher P. Faraboschi G. Desoli Hewlett Packard Laboratories Cambridge MA USA

ISBN: (纸本)9780818676413

In this paper we report on a system which automatically designs realistic VLIW architectures highly optimized for one given application (the input for this system), while running all other code correctly. the system uses a product-quality compiler that generates very aggressive VLIW code. We retarget the compiler until we have found a VLIW architecture idealized for the application on the basis of performance, a cost function and a hardware budget. We show that we can automatically select architectures that achieve large speedups on color and image processing codes. Specialization is shown to be very valuable: the differences between architectural choices, even among reasonable-seeming architectures having similar costs, can be very great, often a factor of 5 (and sometimes much more). We show also that specialization is also very dangerous. A reasonable choice of architecture to fit one algorithm can be a very poor choice for another even in the same domain. there is sometimes an architecture, near in cost and performance to the best, that does much better on a second algorithm.

关键词： Microprocessors VLIW Silicon Process design Laboratories Design optimization Cost function Hardware Color Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures 29

A persistent rescheduled-page cache for low overhead object ...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： T.M. Conte S.W. Sathaye S. Banerjia Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

ISBN: (纸本)9780818676413

Object-code compatibility between processor generations is an open issue for VLIW architectures. A potential solution is a technique termed dynamic rescheduling, which performs run-time software rescheduling at the first-time page faults. the time required for rescheduling the pages constitutes a large portion of the overhead of this method. A disk caching scheme that uses a persistent rescheduled-page cache (PRC) is presented. the scheme reduces the overhead associated with dynamic rescheduling by saving rescheduled pages on disk, across program executions. Operating system support is required for dynamic rescheduling and management of the PRC. the implementation details for the PRC are discussed. Results of simulations used to gauge the effectiveness of PRC indicate that: the PRC is effective in reducing the overhead of dynamic rescheduling; and due to different overhead requirements of programs, a split PRC organization performs better than a unified PRC. the unified PRC was studied for two different page replacement policies: LRU and overhead-based replacement. It was found that with LRU replacement, all the programs consistently perform better with increasing PRC sizes, but the high-overhead programs take a consistent performance hit compared to the low-overhead programs. With overhead-based replacement, the performance of high-overhead programs improves substantially, while the low-overhead programs perform only slightly worse than in the case of the LRU replacement.

关键词： VLIW Partial response channels Hardware Computer architecture Processor scheduling Runtime Operating systems Dynamic scheduling Delay Program processors

来源：评论

学校读者我要写书评

暂无评论

PARALLEL algorithms AND architectures FOR RULE-BASED SYSTEMS.

PARALLEL ALGORITHMS AND ARCHITECTURES FOR RULE-BASED SYSTEMS...

引用

13th Annual International symposium on Computer Architecture - Conference proceedings.

作者： Gupta, Anoop Forgy, Charles Newell, Allen Wedig, Robert Carnegie-Mellon Univ Pittsburgh PA USA Carnegie-Mellon Univ Pittsburgh PA USA

ISBN: (纸本)081860719X

Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from parallelism is quite limited, less than 10-fold. the reasons for the small speedup are: (1) the small number of rules relevant to each change to data memory;(2) the large variation in the processing required by the relevant rules;and (3) the small number of changes made to data memory between synchronization steps. To obtain this limited factor of 10-fold speedup, it is necessary to exploit parallelism at a very fine granularity. It is suggested that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/s. this speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.

关键词： Computer systems, Digital

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共5页 << < 1 2 3 4 5 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：