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Annual ACM symposium on parallelism in algorithms and architectures

Annual ACM symposium on parallelism in algorithms and archit...

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30th ACM symposium on parallelism in algorithms and architectures, SPAA 2018

ISBN: (纸本)9781450357999

the proceedings contain 47 papers. the topics discussed include: parallel minimum cuts in near-linear work and low depth;trees for vertex cuts, hypergraph cuts and minimum hypergraph bisection;dynamic representations of sparse distributed networks: a locality-sensitive approach;constant-depth and subcubic-size threshold circuits for matrix multiplication;integrated model, batch, and domain parallelism in training neural networks;brief announcement: on approximating pagerank locally with sublinear query complexity;brief announcement: coloring-based task mapping for dragonfly systems;brief announcement: parallel transitive closure within 3D crosspoint memory;and lock-free contention adapting search trees.

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A Comparison of High-Level Programming Choices for Incomplete Sparse Factorization Across Different architectures 30

A Comparison of High-Level Programming Choices for Incomplet...

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30th IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Booth, Joshua Dennis Kim, Kyungjoo Rajamanickam, Sivasankaran Sandia Natl Labs Ctr Res Comp POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781509036820

All many-core systems require fine-grained shared memory parallelism, however the most efficient way to extract such parallelism is far from trivial. Fine-grained parallel algorithms face various performance trade-offs related to tasking, accesses to global data-structures, and use of shared cache. While programming models provide high level abstractions, such as data and task parallelism, algorithmic choices still remain open on how to best implement irregular algorithms, such as sparse factorizations, while taking into account the trade-offs mentioned above. In this paper, we compare these performance trade-offs for task and data parallelism on different hardware architectures such as Intel Sandy Bridge, Intel Xeon Phi, and IBM Power8. We do this by comparing the scaling of a new task-parallel incomplete sparse Cholesky factorization called Tacho and a new data-parallel incomplete sparse LU factorization called Basker. Both solvers utilize Kokkos programming model and were developed within the ShyLU package of Trilinos. Using these two codes we demonstrate how high-level programming changes affect performance and overhead costs on multiple multi/many-core systems. We find that Kokkos is able to provide comparable performance with both parallel_for and task/futures on traditional x86 multicores. However, the choice of which high-level abstraction to use on many-core systems depends on both the architectures and input matrices.

关键词： Performance Programming Models Sparse Factorizations Sparse Linear Algebra

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Dual-Purpose Hardware algorithms and architectures - Part 1: Floating-Point Division 30

Dual-Purpose Hardware Algorithms and Architectures - Part 1:...

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30th IEEE symposium on Computer Arithmetic (ARIth)

作者： Seo, Jihee Kim, Dae Hyun Synopsys Inc Hillsboro OR 97124 USA Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99163 USA

ISBN: (纸本)9798350319224

Division is a time-consuming, but frequently-used arithmetic operation, so an enormous amount of effort has been made to improve the performance of dividers. Most of the division algorithms in the literature are offline algorithms that minimize the execution time of a single division, whereas some others are online algorithms that maximize the throughput (# divisions executed per time). In this paper, we propose an interval-analysis-based normal-binary floating-point division algorithm that can be used for both offline and online division. We implement two offline and four online dividers using the algorithm and compare them with recently-proposed offline and online dividers. the simulation results show that the offline versions are the best for a Binary64 offline division, whereas the online versions are the best for a Binary64 online division.

关键词： Divider Floating-Point Arithmetic Online Division

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Dual-Purpose Hardware algorithms and architectures - Part 2: Integer Division 30

Dual-Purpose Hardware Algorithms and Architectures - Part 2:...

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30th IEEE symposium on Computer Arithmetic (ARIth)

作者： Seo, Jihee Kim, Dae Hyun Synopsys Inc Hillsboro OR 97124 USA Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99163 USA

ISBN: (纸本)9798350319224

Integer division is different from floating-point division in that (1) the execution time of an integer division is highly dependent on the leading 1 locations of operands, (2) x and -x have different magnitude parts if x is a two's complement integer, and (3) rounding is not necessary. In this paper, we apply the interval-analysis-based division algorithm proposed in "Dual-Purpose Hardware algorithms and Architecture - Part 1: Floating-Point Division" [1] to offline and online integer division. We implement four online integer dividers using the algorithm, compare them with other dividers, and present detailed simulation results with in-depth analysis of the dividers. We find that the online dividers outperform the offline dividers when the waiting time for online operands goes up and the number of quotient bits to obtain goes down.

关键词： Divider Integer Arithmetic Online Division

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proceedings - 2023 IEEE 30th symposium on Computer Arithmetic, ARIth 2023

Proceedings - 2023 IEEE 30th Symposium on Computer Arithmeti...

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30th IEEE symposium on Computer Arithmetic, ARIth 2023

ISBN: (纸本)9798350319224

the proceedings contain 25 papers. the topics discussed include: LAProof: a library of formal proofs of accuracy and correctness for linear algebra programs;a multiplier-free RNS-based CNN accelerator exploiting bit-level sparsity;exact fused dot product add operator;extracting low-precision floating-point adders from embedded hard FP DSP blocks on FPGAs;formal verification of floating-point division;dual-purpose hardware algorithms and architectures – part 2: integer division;Newton-Raphson integer division for area-constrained microcontrollers;scalable architecture of constant division on FPGA;and dual-purpose hardware algorithms and architectures – part 1: floating-point division.

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Parallel Graph Coloring for Manycore architectures 30

Parallel Graph Coloring for Manycore Architectures

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30th IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Deveci, Mehmet Boman, Erik G. Devine, Karen D. Rajamanickam, Sivasankaran Sandia Natl Labs POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781509021406

Graph algorithms are challenging to parallelize on manycore architectures due to complex data dependencies and irregular memory access. We consider the well studied problem of coloring the vertices of a graph. In many applications it is important to compute a coloring with few colors in near-linear time. In parallel, the optimistic (speculative) coloring method by Gebremedhin and Manne [1] is the preferred approach but it needs to be modified for manycore architectures. We discuss a range of implementation issues for this vertex-based optimistic approach. We also propose a novel edge-based optimistic approach that has more parallelism and is better suited to GPUs. We study the performance empirically on two architectures (Xeon Phi and GPU) and across many data sets (from finite element problems to social networks). Our implementation uses the Kokkos library, so it is portable across platforms. We show that on GPUs, we significantly reduce the number of colors (geometric mean 4X, but up to 48X) as compared to the widely used cuSPARSE library. In addition, our edge-based algorithm is 1.5 times faster on average than cuSPARSE, where it has speedups up to 139X on a circuit problem. We also show the effect of the coloring on a conjugate gradient solver using multi-colored Symmetric Gauss-Seidel method as preconditioner;the higher coloring quality found by the proposed methods reduces the overall solve time up to 33% compared to cuSPARSE.

关键词： coloring combinatorial scientific computing GPU Xeon Phi manycore

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proceedings - 2019 IEEE 30th International symposium on Software Reliability Engineering Workshops, ISSREW 2019

Proceedings - 2019 IEEE 30th International Symposium on Soft...

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30th IEEE International symposium on Software Reliability Engineering Workshops, ISSREW 2019

ISBN: (纸本)9781728151380

the proceedings contain 77 papers. the topics discussed include: software framework for data fault injection to test machine learning systems;MemDefender: an allocation monitoring and memory leak injection tool for java;anomaly detection as-a-service;avoiding faults due to dangling dependencies by synchronization in microservices applications;applying modified code entity-based regression test selection for manual end-to-end testing of commercial web applications;concurrency defect localization in embedded systems using static code analysis: an evaluation;engineering and hardening of functional fail-operational architectures for highly automated driving;and detecting and diagnosing anomalous behavior in large systems with change detection algorithms.

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Efficient Error-Bounded Lossy Compression for CPU architectures 30

Efficient Error-Bounded Lossy Compression for CPU Architectu...

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30th International symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Dube, Griffin Tian, Jiannan Di, Sheng Tao, Dingwen Calhoun, Jon C. Cappello, Franck Northwestern Univ Dept Comp Sci Evanston IL 60208 USA Indiana Univ Luddy Sch Informat Comp & Engn Bloomington IN 47408 USA Argonne Natl Lab Math & Comp Sci Div Lemont IL 60439 USA Clemson Univ Holcombe Dept Elect & Comp Engn Clemson SC 29634 USA

ISBN: (纸本)9781665455800

Modern HPC applications produce increasingly large amounts of data, which limits the performance of current extreme-scale systems. Lossy compression, helps to mitigate this issue by decreasing the size of data generated by these applications. SZ, a current state-of-the-art lossy compressor, is able to achieve high compression ratios, but its prediction/quantization methods contain RAW dependencies that prevent parallelizing this step of the compression. Recent work proposes a parallel dual prediction/quantization algorithm for GPUs which removes these dependencies. However, some HPC systems and applications do not use GPUs, and could still benefit from the fine-grained parallelism of this method. Using the dual-quantization technique, we implement and optimize a SIMD vectorized CPU version of SZ (vecSZ), and create a heuristic for selecting the optimal block size and vector length. We propose a novel block padding algorithm to decrease the number of unpredictable values along compression block borders and find it reduces the number of prediction outliers by up to 100%. We measure performance of our vecSZ against an CPU version of SZ using dual-quantization, pSZ, as well as SZ-1.4. Using real-world scientific datasets, we evaluate vecSZ on the Intel Skylake and AMD Rome architectures. vecSZ results in up to 32% improvement in rate-distortion and up to 15x speedup over SZ-1.4, achieving a prediction and quantization bandwidth in excess of 3.4 GB/s.

关键词： lossy compression compression big data vectorization program optimization

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A review of in-memory computing architectures for machine learning applications 20

A review of in-memory computing architectures for machine le...

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30th Great Lakes symposium on VLSI, GLSVLSI 2020

作者： Bavikadi, Sathwika Sutradhar, Purab Ranjan Khasawneh, Khaled N. Ganguly, Amlan Dinakarrao, Sai Manoj Pudukotai Department of Electrical and Computer Engineering George Mason University FairfaxVA United States Department of Computer Engineering Rochester Institute of Technology RochesterNY United States

ISBN: (纸本)9781450379441

the state-of-the-art traditional computing hardware is struggling to meet the extensive computational load presented by the rapidly growing Machine Learning (ML) and Artificial Intelligence (AI) algorithms such as Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). In order to obtain hardware solutions to meet the low-latency and high-throughput computational demands from these algorithms, Non-Von Neumann computing architectures such as In-memory Computing (IMC)/ Processing-in-memory (PIM) are being extensively researched and experimented with. In this survey paper, we analyze and review pioneer IMC/PIM works designed to accelerate ML algorithms such as DNNs and CNNs. We investigate different architectural aspects and dimensions of these works and provide our comparative evaluations. Furthermore, we discuss challenges and limitations in IMC research and also present feasible directions based on our observations and insight. © 2020 Association for Computing Machinery.

关键词： Deep neural networks

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On the Development of Variable Size Batched Computation for Heterogeneous Parallel architectures 30

On the Development of Variable Size Batched Computation for ...

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30th IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Abdelfattah, Ahmad Haidar, Azzam Tomov, Stanimire Dongarra, Jack Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester Lancs England

ISBN: (纸本)9781509036820

Many scientific applications, ranging from national security to medical advances, require solving a number of relatively small-size independent problems. As the size of each individual problem does not provide sufficient parallelism for the underlying hardware, especially accelerators, these problems must be solved concurrently as a batch in order to saturate the hardware with enough work, hence the name batched computation. A possible simplification is to assume a uniform size for all problems. However, real applications do not necessarily satisfy such assumption. Consequently, an efficient solution for variable-size batched computations is required. this paper proposes a foundation for high performance variable-size batched matrix computation based on Graphics Processing Units (GPUs). Being throughput-oriented processors, GPUs favor regular computation and less divergence among threads, in order to achieve high performance. therefore, the development of high performance numerical software for this kind of problems is challenging. As a case study, we developed efficient batched Cholesky factorization algorithms for relatively small matrices of different sizes. However, most of the strategies and the software developed, and in particular a set of variable size batched BLAS kernels, can be used in many other dense matrix factorizations, large scale sparse direct multifrontal solvers, and applications. We propose new interfaces and mechanisms to handle the irregular computation pattern on the GPU. According to the authors' knowledge, this is the first attempt to develop high performance software for this class of problems. Using a K40c GPU, our performance tests show speedups of up to 2.5x against two Sandy Bridge CPUs (8-core each) running Intel MKL library.

关键词： batched computation GPUs variable small sizes

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