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Bias analysis of AI models for undergraduate student admissions

Neural computing and Applications 2025年第12期37卷 7785-7795页

作者： Van Busum, Kelly Fang, Shiaofen Department of Computer Science and Software Engineering Butler University IndianapolisIN United States Computing and Engineering Indiana University Luddy School of Informatics Indiana University Indianapolis IndianapolisIN United States

Bias detection and mitigation is an active area of research in machine learning. this work extends previous research done by the authors Van Busum and Fang (proceedings of the 38th acm/sigapp symposium on applied computing, 2023) to provide a rigorous and more complete analysis of the bias found in AI predictive models. Admissions data spanning six years was used to create an AI model to determine whether a given student would be directly admitted into the School of Science under various scenarios at a large urban research university. During this time, submission of standardized test scores as part of a student’s application became optional which led to interesting questions about the impact of standardized test scores on admission decisions. We developed and analyzed AI models to understand which variables are important in admissions decisions, and how the decision to exclude test scores affects the demographics of the students who are admitted. We then evaluated the predictive models to detect and analyze biases these models may carry with respect to three variables chosen to represent sensitive populations: gender, race, and whether a student was the first in his/her family to attend college. We also extended our analysis to show that the biases detected were persistent. Finally, we included several fairness metrics in our analysis and discussed the uses and limitations of these metrics. © the Author(s), under exclusive licence to Springer-Verlag London Ltd., part of Springer Nature 2024.

关键词： Students

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ML-QLS: Multilevel Quantum Layout Synthesis 25

ML-QLS: Multilevel Quantum Layout Synthesis

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34th International symposium on Physical Design-ISPD

作者： Lin, Wan-Hsuan Cong, Jason Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9798400712937

Quantum Layout Synthesis (QLS) plays a crucial role in optimizing quantum circuit execution on physical quantum devices. As we enter the era where quantum computers have hundreds of qubits, optimal OLS tools face scalability issues, while heuristic methods suffer significant optimality gap due to the lack of global optimization. To address these challenges, we introduce a multilevel framework, which is an effective methodology for solving large-scale problems in VLSI design. In this paper, we present ML-QLS, the first multilevel quantum layout tool with a scalable refinement operation integrated with novel cost functions and clustering strategies. Our clustering provides valuable insights into generating a proper problem approximation for quantum circuits and devices. the experimental results demonstrate that ML-QLS can scale up to problems involving hundreds of qubits and achieve a remarkable 69% performance improvement over leading heuristic QLS tools for large circuits, which underscores the effectiveness of multilevel frameworks in quantum applications.

关键词： Quantum computing QLS qubit mapping multilevel framework

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A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation 24

A 9 Transistor SRAM Featuring Array-level XOR Parallelism wi...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Yin, Zihan Datta, Annewsha Vijayakumar, Shwetha Jacob, Ajey Jaiswal, Akhilesh Univ Wisconsin Madison Madison WI 53706 USA Univ Southern Calif Los Angeles CA USA Informat Sci Inst Marina Del Rey CA USA

ISBN: (纸本)9798400706059

Security, speed, and energy efficiency are critical for computing applications in general and for edge applications in particular. Digital In-Memory computing (IMC) in SRAM cells has widely been studied to accelerate inference tasks to maximize both throughput and energy efficiency for intelligent computing at the edge. XOR operations have been of particular interest due to their wide applicability in numerous applications that include binary neural networks and encryption. Based on monte-carlo simulation on commercial Globalfoundries 22nm node, we are proposing a novel 9T SRAM cell enabling multiple rows of data (entire array) to be XORed in a massively parallel single cycle fashion, compared to XOR of two rows in prior IMC works. the new cell also supports array-level data-toggling, using the least number of transistors compared to previous works, within the SRAM cell efficiently to circumvent imprinting attacks and erase the SRAM value in case of a remanence attack. Our proposed SRAM thus combines security with in-memory computing while achieving significant area efficiency.

关键词： Static random access memory (SRAM) Security Data Imprinting In-memory computing XOR

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27th International Database Engineered Applications symposium, IDEAS 2023

27th International Database Engineered Applications Symposiu...

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27th International Database Engineered Applications symposium, IDEAS 2023

ISBN: (纸本)9798400707445

the proceedings contain 26 papers. the topics discussed include: discovery of patent influence with directed acyclic graph network analysis;FedShare: secure aggregation based on additive secret sharing in federated learning;enhancing declarative temporal model mining in relational databases: a preliminary study;condensed nearest neighbor rules for multi-label datasets;challenges of spatio-temporal trajectory data use: focus group findings from the 1st International Summer School on Data Science for Mobility;BIOCHAIN: towards a platform for securely sharing microbiological data;very fast variations of training set size reduction algorithms for instance-based classification;bitcoin price prediction considering sentiment analysis on Twitter and Google News;approach considering collective intelligence for interactive web services composition;information visualization for industrial process monitoring;and AdapterEM: pre-trained language model adaptation for generalized entity matching using adapter-tuning.

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Probabilistic Bayesian Neural Networks for Efficient Inference 24

Probabilistic Bayesian Neural Networks for Efficient Inferen...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Ishak, Md Alawad, Mohammed Wayne State Univ Dept Elect & Comp Engn Detroit MI 48202 USA

ISBN: (纸本)9798400706059

Bayesian Neural Networks (BNNs) offer a principled framework for modeling uncertainty in deep learning tasks. However, conventional BNNs often suffer from high computational complexity and parameter overhead. In this paper, we propose a novel approach, termed Probabilistic BNN (ProbBNN), which leverages probabilistic computing principles to streamline the inference process. Unlike traditional deterministic approaches, ProbBNN represents inputs and parameters as random variables governed by probability distributions, allowing for the propagation of uncertainty throughout the network. We employ Gaussian Mixture Models (GMMs) to represent the parameters of each neuron or convolutional kernel, enabling efficient encoding and processing of uncertainty. Our approach simplifies the inference process by replacing complex deterministic computations with lightweight probabilistic operations, resulting in reduced computational complexity and improved scalability. Experimental results demonstrate the effectiveness of ProbBNN in achieving competitive accuracy to traditional BNNs while significantly reducing the number of parameters. the transition to ProbBNN yields a reduction of two orders of magnitude in the number of parameters compared to baseline approaches, making our approach promising for deployment in resource-constrained applications such as edge computing and IoT devices.

关键词： Bayesian neural network probabilistic computing Gaussian Mixture Model

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MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators 24

MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Bai, Jinyu Zhang, He Liu, LongChao Li, Pengfei Kang, Wang Beihang Univ Hangzhou Int Innovat Inst Natl Key Lab Spintron Hangzhou 311115 Peoples R China Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China Beijing Jinghanyu Elect Engn Technol Co Ltd Beijing 102206 Peoples R China

ISBN: (纸本)9798400706059

Quantization is vital for deploying neural networks on computing-In-Memory (CIM) based accelerators due to inherent limitations in memory devices and data interfaces' representational capacities. However, traditional quantization algorithms often overlook CIM's unique computing paradigm, leading to suboptimal performance. To address this, we introduce MixMixQ, a novel quantization algorithm specifically designed for CIM accelerators that strategically integrates mixed bit-sparsity and mixed bit-width, enhancing overall hardware efficiency while preserving high accuracy. Notably, our method can enhance hardware efficiency by up to 294% compared to traditional quantization methods, with only a minimal 0.13% decrease in accuracy compared to a full-precision network.

关键词： computing-In-Memory Neural Network Quantization Bit-Sparsity Gradient Estimation Evolutionary Algorithm

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Security assessment of a commercial router using physical access: a case study 34

Security assessment of a commercial router using physical ac...

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34th International Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype

作者： Stephenne, Colin de Magalhaes, Felipe Cuppens, Frederic Ouattara, Jean-Yves Jean, Militza Fernandez, Jose Nicolescu, Gabriela Polytech Montreal Montreal PQ Canada CyberPNM Montreal PQ Canada Cybereco Montreal PQ Canada

ISBN: (纸本)9798400704109

Physical access to a device can greatly help in vulnerability research as it opens up new vectors for exploitation. this is especially true for embedded devices, which often come with open serial ports and various types of debugging features. therefore, security assessments of these devices should take into consideration the hardware components and their means of communication. In this paper, we explore a testing methodology that transforms a black box test into a white box test by using physical access to retrieve the code of the applications running on the device. To demonstrate its advantages, we apply this methodology to assess the security risks on a commercial router. We use it to uncover multiple code execution vulnerabilities in the router's firmware. We discuss secure coding guidelines to remediate those vulnerabilities and the importance of IoT security.

关键词： IoT Internet of things Router security Trusted computing

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Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on computing 24

Hybrid Magneto-electric FET-CMOS Integrated Memory Design fo...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Najafi, Deniz Tabrizchi, Sepehr Zhou, Ranyang Solouki, Mohammadreza Amel Marshall, Andrew Roohi, Arman Angizi, Shaahin New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA Univ Nebraska Lincoln Sch Comp Lincoln NE USA Politecn Torino Dept Control & Comp Engn Turin Italy Univ Texas Dallas Dept Elect & Comp Engn Dallas TX USA

ISBN: (纸本)9798400706059

the surge in the number of normally-off power-constraint Internet of things (IoT) devices in recent years has amplified the demand for high-performance and energy-efficient in-memory computing architectures built on top of various non-volatile memories. MagnetoElectric Field Effect Transistors (MEFETs) have presented compelling design features suitable for logic and memory integration as an emerging post-CMOS FET. these include high-speed switching, minimal power usage, and non-volatility. this work introduces a new in-memory computing architecture designed for edge applications, leveraging emerging MEFETs. the proposed architecture enables the execution of both Boolean logic operations and Binary Content Addressable Memory (BCAM) operations within a single cycle. Furthermore, the energy consumption during the write operation of the proposed cell is optimized by introducing a new write circuitry. the outcomes of our device-to-architecture evaluation reveal approximately 43.5% and 96.9% reduction in read and write energy consumption, respectively, compared to the counterpart non-volatile memories. At the application level, the proposed architecture is applied to implement Binary Neural Networks (BNNs) based on AlexNet and VGG16. Our results showcase a decrease of approximately 54% in the overall energy consumption when implementing these networks using the proposed design compared to non-volatile in-memory computing designs.

关键词： Energy utilization

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A New Routing Strategy to Improve Success Rates of Quantum Computers 24

A New Routing Strategy to Improve Success Rates of Quantum C...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Qi, Fang Fu, Xin Yuan, Xu Tzeng, Nian-Feng Peng, Lu Tulane Univ New Orleans LA 70118 USA Univ Houston Houston TX USA Univ Delaware Newark DC USA Univ Louisiana Lafayette Lafayette LA USA

ISBN: (纸本)9798400706059

In the current noisy intermediate-scale quantum (NISQ) Era, Quantum computing faces significant challenges due to noise, which severely restricts the application of computing complex algorithms. Superconducting quantum chips, one of the pioneer quantum computation technologies, introduce additional noise when moving qubits to adjacent locations for operation on designated two-qubit gates. the current compilers rely on decision models that either count the swap gates or multiply the gate errors when choosing swap paths at the routing stage. Our research has unveiled the overlooked situations for error propagations through the circuit, leading to accumulations that may affect the final output. In this paper, we propose Error Propagation-Aware Routing (EPAR), designed to enhance the compilation performance by considering accumulated errors in routing. EPAR's effectiveness is validated through benchmarks on a 27-qubit machine and two simulated systems with different topologies. the results indicate an average success rate improvement of 10% on both real and simulated heavy hex lattice topologies, along with a 16% enhancement in a mesh topology simulation. these findings underscore the potential of EPAR to advance quantum computing in the NISQ era substantially.

关键词： Quantum computing Routing Compilation Performance

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Toward Fair Ultrasound computing Tomography: Challenges, Solutions and Outlook 24

Toward Fair Ultrasound Computing Tomography: Challenges, Sol...

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34th Great Lakes symposium on VLSI (GLSVLSI)

作者： Sheng, Yi Yang, Junhuan Lin, Youzuo Jiang, Weiwen Yang, Lei George Mason Univ Fairfax VA 22030 USA

ISBN: (纸本)9798400706059

Medical image reconstruction plays a pivotal role in early cancer detection, which can significantly enhance both the quality and longevity of a patient's life through timely treatment. However, the extent to which current image reconstruction methods accurately represent all populations, and whether they underperform for certain groups, remains largely unexplored. In this work, we will examine the deep learning (DL)-based approach to image reconstruction and its associated fairness concerns. Initially, our experiments confirmed the unfairness's presence. Subsequently, by addressing the issue from two perspectives, we gained valuable insights, which deepened our understanding of the problem. To assess a model's fairness, it's crucial to evaluate it from various perspectives, as relying on a single metric can often yield misleading results.

关键词： USCT Image Reconstruction Fairness InversionNet

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