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A unified analysis of hot video schedulers

A unified analysis of hot video schedulers

引用

proceedings of the 34th Annual acm symposium on theory of computing

作者： Chan, Wun-Tat Lam, Tak-Wah Ting, Hing-Fung Wong, Wai-Ha Department of Computing Hong Kong Polytechnic University Hong Kong Hong Kong

In this paper we consider the notion of relative competitive analysis, which is a simple generalization of the conventional competitive analysis and extra-resource analysis for on-line algorithms. We apply this analysis to study on-line schedulers for stream merging in two different video-on-demand (VOD) systems, which are based on two common approaches, namely, piggybacking and skimming. Our new analysis, in its simplest form, reveals a 3-competitive algorithm for stream merging based on skimming as well as piggybacking. this improves all previous results [4, 8]. We also show how to obtain guarantee on the performance improvement based on adding extra resources, and more interestingly, we provide a unified methodology to compare piggybacking and skimming. We believe that our result gives a clue to system designers for choosing desirable configurations.

关键词： Computation theory

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Emerging applications for the connected home

Emerging applications for the connected home

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： A. Wolfe SONICBlue Inc.

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Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)

Mapping reference code to irregular DSPs within the retarget...

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： G.W. Grewal C.T. Wilson Department of Computing and Information Science University of Guelph Guelph ONT Canada

Generating high quality code for embedded processors is made difficult by irregular architectures and highly encoded parallel instructions. Rather than deal with the target machine at every stage of the compilation, a promising new methodology employs generic algorithms to optimize code for an idealized abstraction of the true target machine. this code, called reference code, is then mapped to the real instruction set by enhanced genetic algorithms. One perturbs the original schedule to find a number of alternative (parallel) instruction sequences, and the other evolves feasible register assignments, if possible, for each sequence. this paper describes the strategy for mapping idealized code into actual code. the COGEN(T) system employs this methodology to produce good code for different commercial DSPs and ASIPs.

关键词： Digital signal processing Optimizing compilers Application specific processors Instruction sets Registers Computer aided instruction Concurrent computing Embedded computing Information science Computer architecture

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Performance characterization of a hardware mechanism for dynamic optimization

Performance characterization of a hardware mechanism for dyn...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： B. Fahs S. Bose M. Crum B. Slechta F. Spadini T. Tung S.J. Patel S.S. Lumetta Center for Reliable and High performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign USA

We evaluate the rePLay microarchitecture as a means for reducing application execution time by facilitating dynamic optimization. the framework contains a programmable optimization engine coupled with a hardware-based recovery mechanism. the optimization engine enables the dynamic optimizer to run concurrently with program execution. the recovery mechanism enables the optimizer to make speculative optimizations without requiring recovery code. We demonstrate that a rePLay configuration performing a small suite of simple optimizations on Alpha code attains an average of 13% reduction in execution cycles on the SPEC2000 integer benchmarks over a rePLay configuration not performing optimizations, and a 21% reduction over an aggressive standard superscalar microarchitecture.

关键词： Hardware Microarchitecture Engines Application software Code standards Libraries Performance analysis Solids Prototypes Instruction sets

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Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

Exploiting VLIW schedule slacks for dynamic and leakage ener...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： W. Zhang N. Vijaykrishnan M. Kandemir M.J. Irwin D. Duarte Y.-F. Tsai Microsystems Design Laboratory Pennsylvania State University University Park PA USA

the mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period. this brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule stacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. the proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.

关键词： VLIW Dynamic scheduling Energy consumption Processor scheduling Circuit simulation Dynamic voltage scaling Clocks Mobile computing Economic forecasting Computer architecture

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Enhancing loop buffering of media and telecommunications applications using low-overhead predication

Enhancing loop buffering of media and telecommunications app...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： J.W. Sias H.C. Hunter W.-M.W. Hwu Center for Reliable and High Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign USA

Media- and telecommunications-focused processors, increasingly designed as deeply pipelined, statically-scheduled VLIWs, rely on loop buffers for low-overhead execution of simple loops. Key loops containing control flow pose a substantial problem-full predication has a high encoding overhead, and partial predication techniques do not support if-conversion, the transformation of general acyclic control flow into predicated blocks. Using a set of significant media processing benchmarks, drawn from MediaBench and contemporary telecommunications standards, we explore a compromise approach. We demonstrate a compiler using if-conversion and specialized loop transformations to arrange for 70-99% of fetched operations to come from a simple, statically managed 256-instruction loop buffer, saving instruction fetch power and eliminating branch penalties. To complement this we introduce a "niche" form of predication specialized to permit general if-conversion with only a single bit in the encoding of each operation and to eliminate much of the hardware overhead of a predicate register-based approach.

关键词： Telecommunication control Kernel Application software VLIW Telecommunication computing Process design Processor scheduling Telecommunication standards Energy management Encoding

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Modulo schedule buffers

Modulo schedule buffers

引用

IEEE/acm International symposium on Microarchitecture (MICRO)

作者： M.C. Merten W.-M.W. Hwu Center for Reliable and High Performance Computing University of Illinois Urbana IL USA

As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of. minimizing code size and reducing power is growing. this paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernel-only modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the predicate register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation.

关键词： Kernel Pipeline processing Processor scheduling Hardware Registers Delay Computer architecture VLIW Application software Software maintenance

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Select-free instruction scheduling logic

Select-free instruction scheduling logic

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： M.D. Brown J. Stark Y.N. Patt Department of Electrical and Computer Engineering University of Texas Austin USA Microprocessor Research Laboratories Intel Corporation USA

Pipelining allows processors to exploit parallelism. Unfortunately, critical loops-pieces of logic that must evaluate in a single cycle to meet IPC (Instructions Per Cycle) goals-prevent deeper pipelining. In today's processors, one of these loops is the instruction scheduling (wakeup and select) logic [10]. this paper describes a technique that pipelines this loop by breaking it into two smaller loops: a critical, single-cycle loop for wakeup; and a noncritical, potentially multi-cycle, loop for select. For the 12 SPECint*2000 benchmarks, a machine with two-cycle select logic (i.e., three-cycle scheduling logic) using this technique has an average IPC 15% greater than a machine with three-cycle pipelined conventional scheduling logic, and an IPC within 3% of a machine of the same pipeline depth and one-cycle (ideal) scheduling logic. Since select accounts for more than half the scheduling latency [10], this technique could significantly increase clock frequency while having minimal impact on IPC.

关键词： Logic Pipeline processing Processor scheduling Clocks Frequency Parallel processing Delay Trademarks Concurrent computing Microprocessors

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Speculative lock elision: enabling highly concurrent multithreaded execution

Speculative lock elision: enabling highly concurrent multith...

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IEEE/acm International symposium on Microarchitecture (MICRO)

作者： R. Rajwar J.R. Goodman Computer Sciences Department University of Wisconsin Madison Madison WI USA

Serialization of threads due to critical sections is a fundamental bottleneck to achieving high performance in multithreaded programs. Dynamically, such serialization may be unnecessary because these critical sections could have safely executed concurrently without locks. Current processors cannot fully exploit such parallelism because they do not have mechanisms to dynamically detect such false inter-thread dependences. We propose Speculative Lock Elision (SLE), a novel micro-architectural technique to remove dynamically unnecessary lock-induced serialization and enable highly concurrent multithreaded execution. the key insight is that locks do not always have to be acquired for a correct execution. Synchronization instructions are predicted as being unnecessary and elided. this allows multiple threads to concurrently execute critical sections protected by the same lock. Misspeculation due to inter-thread data conflicts is detected using existing cache mechanisms and rollback is used for recovery. Successful speculative elision is validated and committed without acquiring the lock. SLE can be implemented entirely in microarchitecture without instruction set support and without system-level modifications, is transparent to programmers, and requires only trivial additional hardware support. SLE can provide programmers a fast path to writing correct high-performance multithreaded programs.

关键词： Yarn Programming profession Reactive power Hardware Data structures High performance computing Parallel processing Protection Microarchitecture Writing

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Explorative modeling for prioritizing liver transplantation waiting lists

Explorative modeling for prioritizing liver transplantation ...

引用

Annual symposium on Simulation

作者： T. Eldabi R. Macredie R.J. Paul Centre for Applied Simulation Modelling Department of Information Systems and Computing Brunei University Uxbridge Middlesex UK

ISBN: (纸本)0769510922

Health care systems are known to be quite complex in structure and operation. the technology of liver transplantation is one of the aspects of health care systems that has always been difficult to grasp. the main problem with liver transplantation is the fact that it is not easy to study using traditional quantitative tools. the paper demonstrates the use of discrete event simulation as an explorative tool to help stakeholders to understand the behavior of the system so that they can achieve informed decisions with regard to the prioritization of patients waiting for transplantation. the paper also shows the construction of a tailor-made package (LiverSim) and provides an example of how this package is used by the stakeholders to assist in the evaluation process. Some final lessons are drawn that simulation helps in exploring more issues outside the boundaries of quantitative results.

关键词： Liver diseases Medical services Discrete event simulation Packaging Europe Decision making Computational modeling Information systems Performance evaluation Hospitals

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