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检索条件"任意字段=Proceedings of the 34th Annual ACM/IEEE Symposium on Logic in Computer Science"

共 360 条记录，以下是181-190 订阅

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Work in progress - Employing a learning model on a traditional engineering course

Work in progress - Employing a learning model on a tradition...

引用

34th annual Frontiers in Education: Expanding Educational Opportunities through Partnerships and Distance Learning - Conference proceedings, FIE

作者： Brown, Cordelia M. Brodersen, Arthur J. Vanderbilt University Electrical Engineering and Computer Science Nashville TN 37235

this paper explores the development of a general learning model that uses as a test bed a course on the introduction to digital logic. the learning model is based on techniques validated by researchers Richard Felder, Eric Mazur, John Bransford, and Shelia Tobias. the learning model features a weekly learning session, structured collaborative laboratory sessions, and challenge projects. A comparative research study is being conducted at Vanderbilt University School of Engineering (VUSE). the study contrasts the traditional instructional with the learning model. the traditionally instructed sections will primarily receive lecture-based instruction. Surveys from students, instructors, and teaching assistants will be used as a means of monitoring the effectiveness of the instructional method used. the study will evaluate the students' performance, attitude toward their instruction, retention, success rate, failure rate, and confidence levels of students in both the traditionally taught sections and the modified instruction sections. through this study, strategies will be developed an effective model for instruction studying laboratory-based engineering courses. Preliminary results for the study conducted in the Spring 2004 will be presented. © 2004 ieee.

关键词： Engineering education

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A systolic parallel multiplier over GF(3m) using neuron-MOS DLC

A systolic parallel multiplier over GF(3m) using neuron-MOS ...

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proceedings - 34th International symposium on Multiple-Values logic, ISMVL 2004

作者： Yoon, Byoung Hee Han, Sung Il Choi, Young-Hee Hwang, Jong-Hak Seong, Hyeon-Kyeong Kim, Heung Soo Department of Electronic Engineering Inha University Incheon 402-751 Korea Republic of Dept. of Sports Engineering Korea Sport Science Institute 223-19 Seoul Korea Republic of Sch. of Comp./Info. Engineering Sangji Univ.

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over GF(3 m), has been proposed using neuron-MOS Down-literal circuit on voltage mode. the three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. the proposed circuits are simulated with the electrical parameter of a standard 0.35§> CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHz sampling rate and maintains output voltage level in ±0.1V.

关键词： Mathematical programming

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Panel - HP-funded engineering retention initiative: Methodologies and findings of four diverse universities/colleges

Panel - HP-funded engineering retention initiative: Methodol...

引用

34th annual Frontiers in Education: Expanding Educational Opportunities through Partnerships and Distance Learning - Conference proceedings, FIE

作者： Brooks, Sandy Brown, Susan W. Mack, Pamela Moya, John Oakes, William HP Philanthropy and Education College of Education New Mexico State University United States College of Engineering Morgan State University United States Department of Electrical and Computer Engineering University of Texas El Paso United States Department of Freshman Engineering Purdue University United States

Hewlett Packard (HP) Philanthropy and ' Education has a long and distinguished history of providing resources to improve education. Most recently, HP created an initiative that invites universities to transform engineering and computer science gatekeeper courses into gateways through curriculum reform, technology integration, and/or improved instruction/pedagogy. the initiative is targeted at two- and four-year institutions with which HP currently has a recruiting or research relationship. this panel builds on the HP-hosted, one-day symposium that was held at the 2003 FIE Conference that convened over 35 HP partner institutions and will include four institutions that demonstrated significant progress in improving targeted course(s) through innovation in curriculum reform, technology integration, and/or improved instruction /pedagogy. Each of the panel members will present an overview of the curriculum redesign, outcomes, and findings of their work. the proposed session will provide a venue for the audience to engage in meaningful dialogue with the panel members and other audience members. © 2004 ieee.

关键词： Engineering education

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Control flow optimization via dynamic reconvergence prediction 37

Control flow optimization via dynamic reconvergence predicti...

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37th International symposium on Microarchitecture - MICRO-37 2004

作者： Collins, Jamison D. Tullsen, Dean M. Wang, Hong Department of Computer Science and Engineering University of California San Diego San Diego CA 92093-0114 United States Microarchitecture Research Labs Intel Corporation Santa Clara CA 95052 United States

ISBN: (纸本)0769521266

this paper presents a novel microarchitecture technique for accurately predicting control flow reconvergence dynamically. A reconvergence point is the earliest dynamic instruction in the program where we can expect program paths to reconverge regardless of the outcome or target of the current branch. thus, even if the immediate control flow after a branch is uncertain, execution following the reconvergence point is certain. this paper proposes a novel hardware reconvergence predictor which is both implementable and accurate, with a 4KB predictor achieving more than 95% accuracy for SPEC INT, and larger implementations achieving greater than 99% accuracy. the information provided from reconvergence prediction can increase the effectiveness of a range of previously proposed performance optimizations, including speculative multithreading, control independence, and squash reuse. this paper also demonstrates a new technique that takes advantage of the dynamic reconvergence prediction information in order to predict a wrong path excursion ahead of branch resolution. On average, 34% of wrong path fetches are eliminated. © 2004 ieee.

关键词： Flow control

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Banked multiported register files for high-frequency superscalar microprocessors 03

Banked multiported register files for high-frequency supersc...

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30th annual International symposium on computer Architecture

作者： Tseng, Jessica H. Asanović, Krste MIT Laboratory for Computer Science 200 Technology Square Cambridge MA 02139 United States

ISBN: (纸本)9780769519456

Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die area. We examine the designs of banked multiported register files that employ multiple interleaved banks of fewer ported register cells to reduce power and area. Banked register files designs have been shown to provide sufficient bandwidth for a superscalar machine, but previous designs had complex control structures that would likely limit cycle time and add to design complexity. We develop a banked register file with much simpler and faster control logic while only slightly increasing the number of ports per bank. We present area, delay, and energy numbers extracted from layouts of the banked register file. For a four-issue superscalar processor, we show that we can reduce area by a factor of three, access time by 20%, and energy by 40%, while decreasing IPC by less than 5%.

关键词： Microprocessor chips

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Fast secure processor for inhibiting software piracy and tampering 36

Fast secure processor for inhibiting software piracy and tam...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： Jun Yang Youtao Zhang Lan Gao Computer Science and Engineering Department University of California Riverside CA USA Computer Science Department University of Texas Dallas Richardson TX USA

ISBN: (纸本)9780769520438

Due to the widespread software piracy and virus attacks, significant efforts have been made to improve security for computer systems. For stand-alone computers, a key observation is that other than the processor, any component is vulnerable to security attacks. Recently, an execution only memory (XOM) architecture has been proposed to support copy and tamper resistant software by D. Lie et al. (2000), D. Lie et al. (2003) and T. Gilmont et al. (1999). In this design, the program and data are stored in encrypted format outside the CPU boundary. the decryption is carried after they are fetched from memory, and before they are used by the CPU. As a result, the lengthened critical path causes a serious performance degradation. In this paper, we present an innovative technique in which the cryptography computation is shifted off from the memory access critical path. We propose to use a different encryption scheme, namely "one-time pad" encryption, to produce the instructions and data ciphertext. With some additional on-chip storage, cryptography computations are carried in parallel with memory accesses, minimizing performance penalty. We performed experiments to study the trade-off between storage size and performance penalty. Our technique improves the execution speed of the XOM architecture by 34% at maximum.

关键词： computer crime Cryptography computer security computer architecture Central Processing Unit Data security Memory architecture Immune system Degradation Concurrent computing

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Lower bounds on the bounded coefficient complexity of bilinear maps

Lower bounds on the bounded coefficient complexity of biline...

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43rd annual ieee symposium on Foundations of computer science

作者： Bürgisser, P Lotz, M Univ Gesamthsch Paderborn Dept Math & Comp Sci D-33095 Paderborn Germany

ISBN: (纸本)0769518222

We prove lower bounds of order n log n for both the problem to multiply polynomials of degree n, and to divide polynomials with remainder in the model of bounded coefficient arithmetic circuits over the complex numbers. these lower bounds are optimal up to order of magnitude. the proof uses a recent idea of R. Raz [Proc. 34th STOC 2002] proposed for matrix multiplication. It reduces the linear problem to multiply a random circulant matrix with a vector to the bilinear problem of cyclic convolution. We treat the arising linear problem by extending J. Morgenstern's bound [J. acm 20, pp. 305-306, 1973] in a unitarily invariant ways this establishes a new lower bound on the bounded coefficient complexity of linear forms in terms of the singular values of the corresponding matrix.

关键词： computer science

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Characterizing and predicting value degree of use 35

Characterizing and predicting value degree of use

引用

35th annual ieee/acm International symposium on Microarchitecture

作者： Butts, JA Sohi, GS Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)0769518591

A value's degree of use-the number of dynamic uses of that value-provides the most essential information needed to optimize its communication. We present simulation results demonstrating the properties of degree of use of values, including their predictability: most static instructions generate values with few degrees of use and these exhibit temporal locality. We use these results to guide the design of a degree of use predictor. the development and detailed characterization of this predictor is the focus of this paper. Our predictor leverages future control flow information (e.g., branch predictions) to select among different possible degrees of use. We study the effects of several optimizations and variations in the predictor's algorithms to tune the predictor for maximum performance. the resulting predictor generates correct degree of use predictions for over 92% of all dynamic values and has a misprediction rate below 2.5%. Such a predictor has a wide range of potential applications in optimizing value communication.

关键词： Bandwidth Computational modeling computer science Delay Design optimization logic Parallel processing Prediction algorithms Predictive models Registers

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Virtual attendance in real engineering lab 34

Virtual attendance in real engineering lab

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34th Southeastern symposium on System theory, SSST 2002

作者： Henry, Jim College of Engineering and Computer Science University of Tennessee at Chattanooga ChattanoogaTN37403 United States

Engineering laboratory equipment at UTC has been made available for users via the World Wide Web. Users can conduct systems lab experiments from remote sites, anytime day-or-night, any day of the week. this paper desc... 详细信息

ISBN: (纸本)0780373391

关键词： Laboratories

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Lower bounds on the bounded coefficient complexity of bilinear maps

Lower bounds on the bounded coefficient complexity of biline...

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annual ieee symposium on Foundations of computer science

作者： P. Burgisser M. Lotz Department of Mathematics and Computer Science University of Paderborn Paderborn Germany

We prove lower bounds of order n log n for both the problem to multiply polynomials of degree n, and to divide polynomials with remainder, in the model of bounded coefficient arithmetic circuits over the complex numbers. these lower bounds are optimal up to order of magnitude. the proof uses a recent idea of R. Raz [Proc. 34th STOC 2002] proposed for matrix multiplication. It reduces the linear problem to multiply a random circulant matrix with a vector to the bilinear problem of cyclic convolution. We treat the arising linear problem by extending J. Morgenstern's bound [J. acm 20, pp. 305-306, 1973] in a unitarily invariant way. this establishes a new lower bound on the bounded coefficient complexity of linear forms in terms of the singular values of the corresponding matrix.

关键词： Circuits Arithmetic Polynomials Vectors Computational modeling Matrix decomposition Convolution Discrete Fourier transforms Mathematics computer science

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