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Managing static leakage energy in microprocessor functional units

Managing static leakage energy in microprocessor functional ...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： S. Dropsho V. Kursun D.H. Albonesi S. Dwarkadas E.G. Friedman Department of Computer Science Department of Electrical and Computer Engineering Department of Computer Science University of Rochester Rochester NY USA Department of Electrical and Computer Engineering University of Rochester Rochester NY USA Department of Electrical and Computer Engineering Department of Computer Science University of Rochester Rochester NY USA

Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed techniques to reduce leakage in on-chip storage structures. In this study, static energy is reduced in the integer functional units by leveraging the unique qualities of dual threshold voltage domino logic. Domino logic has desirable properties that greatly reduce leakage current while providing fast propagation times. However due to the energy cost of entering the low leakage current state (sleep mode), domino logic has thus far been used only for leakage reduction in the longterm standby mode. We examine the utility of the sleep mode (while considering the aforementioned costs) when idle times are relatively short, one to a few hundred cycles, as is often the case for functional units. Using an analytical energy model suitable for architecture-level analysis, we explore the interaction of the application and technology, and the effect on energy and performance as the underlying parameters are varied, on a set of benchmarks. Our results show that if the leakage approaches the magnitude as projected in the literature, even for short idle intervals as few as ten cycles, an aggressive policy of activating the sleep mode at every idle period performs well and a more complex control strategy may not be warranted. We also propose a simple design, called Gradual Sleep, to reduce the energy impact of using the sleep mode for smaller idle periods.

关键词： Energy management Microprocessors Leakage current threshold voltage logic Circuits Subthreshold current Performance analysis CMOS technology Energy dissipation

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Characterizing and predicting value degree of use

Characterizing and predicting value degree of use

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： J.A. Butts G.S. Sohi Computer Science Department University of Wisconsin Madison USA

A value's degree of use - the number of dynamic uses of that value $provides the most essential information needed to optimize its communication. We present simulation results demonstrating the properties of degree of use of values, including their predictability: most static instructions generate values with few degrees of use and these exhibit temporal locality. We use these results to guide the design of a degree of use predictor. the development and detailed characterization of this predictor is the focus of this paper. Our predictor leverages future control flow information (e.g., branch predictions) to select among different possible degrees of use. We study the effects of several optimizations and variations in the predictor's algorithms to tune the predictor for maximum performance. the resulting predictor generates correct degree of use predictions for over 92% of all dynamic values and has a misprediction rate below 2.5%. Such a predictor has a wide range of potential applications in optimizing value communication.

关键词： Design optimization computer science Computational modeling Predictive models Prediction algorithms Parallel processing Registers logic Bandwidth Delay

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three extensions to register integration

Three extensions to register integration

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： V. Petric A. Bracy A. Roth Department of Computer and Information Science University of Pennsylvania USA

Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash reuse, the integration mechanism can exploit more reuse scenarios. Here, we describe three extensions to the original design that expand its applicability and boost its performance impact. First, we extend squash reuse to general reuse. Whereas squash reuse maintains the concept of an instruction instance "owning" its output register, we allow multiple instructions to simultaneously share a single register. Next, we replace the PC-indexing scheme with an opcode-based indexing scheme that exposes more integration opportunities. Finally, we introduce an extension called reverse integration in which we speculatively create integration entries for the inverses of operations for instance, when renaming an add, we create an entry for the inverse subtract. Reverse integration allows us to reuse operations that the program itself has not executed yet. We use reverse integration to implement speculative memory bypassing for stack-pointer based loads (register fills and restores). Our evaluation shows that these extensions increase the integration rate - the number of retired instructions that integrate older results and bypass the execution engine -to an average of 15% on the SPEC2000 integer benchmarks. On a 4-way superscalar processor with an aggressive memory system, this translates into an average IPC improvement of 7%. the fact that integrating instructions completely bypass the execution engine raises the possibility of using integration as a low-complexity substitute for execution bandwidth and issue buffering. Our experiments show that such a trade-off is possible, enabling a range of IPC/complexity designs.

关键词： Testing Registers Microarchitecture Out of order Information science Radio frequency logic Engines Decoding Retirement

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proceedings: 34th acm/ieee international symposium on microarchitecture

Proceedings: 34th ACM/IEEE international symposium on microa...

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34th annual International symposium on Microarchitecture acm/ieee 2001

the proceedings contains 29 papers from the conference of 34th acm/ieee International symposium on Microarchitecture. Topics discussed include: skipper: a microarchitecture for exploiting control-flow independence;performance characterization of a hardware mechanism;a design space evaluation of grid processor architectures;reducing power with dynamic critical path information;direct address caches for reduced power consumption;modulo schedule buffers;select-free instruction scheduling logic;and correctly implementing value prediction in microprocessors.

关键词： computer architecture

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Reducing power with dynamic critical path information

Reducing power with dynamic critical path information

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34th annual International symposium on Microarchitecture acm/ieee 2001

作者： Seng, John S. Tune, Eric S. Tullsen, Dean M. Dept. of Computer Science and Eng. University of California San Diego CA 92093-0114 United States

Recent research has shown that dynamic information regarding instruction criticality can be used to increase microprocessor performance. Critical path information can also be used in processors to achieve a better balance of power and performance. this paper uses the output of a dynamic critical path predictor to decrease the power consumption of key portions of the processor without incurring a corresponding decrease in performance. the optimizations include effective use of functional units with different power and latency characteristics and decreased issue logic power.

关键词： Critical path analysis

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Reducing the complexity of the register file in dynamic superscalar processors

Reducing the complexity of the register file in dynamic supe...

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34th annual International symposium on Microarchitecture acm/ieee 2001

作者： Balasubraamonian, Rajeev Dwarkadas, Sandhya Albonesi, David H. Department of Computer Science University of Rochester Rochester NY United States

Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. the number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register at dispatch. A large multi-ported register file helps improve the instruction-level parallelism (ILP), but may have a detrimental effect on clock speed, especially in future wire-limited technologies. In this paper, we propose a register file organization that reduces register file size and port requirements for a given amount of ILP. We use a two-level register file organization to reduce register file size requirements, and a banked organization to reduce port requirements. We demonstrate empirically that the resulting register file organizations have reduced latency and (in the case of the banked organization) energy requirements for similar instructions per cycle (IPC) performance and improved instructions per second (IPS) performance in comparison to a conventional monolithic register file. the choice of organization is dependent on design goals.

关键词： Program processors

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Saving energy with architectural and frequency adaptations for multimedia applications

Saving energy with architectural and frequency adaptations f...

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34th annual International symposium on Microarchitecture acm/ieee 2001

作者： Hughes, Christopher J. Srinivasan, Jayanth Adve, Sarita V. Department of Computer Science University of Illinois Urbana IL United States

General-purpose processors are expected to be increasingly employed for multimedia workloads on systems where reducing energy consumption is an important goal. Researchers have proposed the use of two forms of hardware adaptation - architectural adaptation and dynamic voltage (and frequency) scaling or DVS - to reduce energy. this paper develops and evaluates an integrated algorithm to control both architectural adaptation and DVS targeted to multimedia applications. It also examines the interaction between the two forms of adaptation, identifying when each will perform better in isolation and when the addition of architectural adaptation will benefit DVS. Our adaptation control algorithm is effective in saving energy and exploits most of the available potential. For the applications and systems studied, DVS is consistently better than architectural adaptation in isolation. the addition of architectural adaptation to DVS benefits some applications, but not all. Finally, in a seemingly counter-intuitive result, we find that while less aggressive architectures reduce energy for fixed frequency hardware, with DVS, more aggressive architectures are often more energy efficient.

关键词： Multimedia systems

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Direct addressed caches for reduced power consumption

Direct addressed caches for reduced power consumption

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34th annual International symposium on Microarchitecture acm/ieee 2001

作者： Witchel, Emmett Larsen, Sam Scott Ananian, C. Asanović, Krste MIT Laboratory for Computer Science Cambridge MA 02139 United States

A direct addressed cache is a hardware-software design for an energy-efficient microprocessor data cache. Direct addressing allows software to access cache data without a hardware cache tag check. these tag-unchecked loads and stores save the energy of a tag check when the compiler can guarantee an access will be to the same line as an earlier access. We have added support for tag-unchecked loads and stores to C and Java compilers. For Mediabench C programs, the compiler eliminates 16-76% of data cache tag accesses, with half of the benchmarks avoiding over 40% of the data tag checks. For SPECjvm98 Java programs, the compiler eliminates 18-63% of data cache tag checks. these tag check reductions translate into data cache energy savings of 9-40%, and overall processor and cache energy savings of 2-8%.

关键词： Cache memory

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Queue structures for shared-memory multiprocessor systems

Queue structures for shared-memory multiprocessor systems

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34th annual Simulation symposium (SS 2001)

作者： Zhu, W. Department of Computer Science University of New South Wales ADFA NSW ACT2600 Australia

three basic structures have been proposed to organize the task queues for shared-memory multiprocessor systems: centralized, distributed, and hierarchical structures. the hierarchical structure intends to combine the advantage of the other two structures and eliminate their disadvantages. Unfortunately, we find it still has serious load imbalancing, in particular when the workload is heavy and irregular. We propose the use of a forest structure in place of a hierarchical one. Simulation shows the proposed structure can provide better load balancing and less contention than the hierarchical one.

关键词： Parallel processing systems

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Performance optimization of throttled time-warp simulation

Performance optimization of throttled time-warp simulation

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34th annual Simulation symposium (SS 2001)

作者： Tay, S.C. Teo, Y.M. Department of Computer Science National University of Singapore 3 Science Drive 2 Singapore 117543 Singapore

While constraining the speculation in Time Warp (TW) tends to decrease the number of false event executions, it also introduces an opportunity cost when the processors are not fully utilized. To obtain good run-time performance such a trade-off must be optimized. this paper studies the implications of regulating speculation in TW, and develops an analytic framework for optimizing the elapsed time of TW simulators. By aggregating the effect of three time components, namely computation time, communication time and processor idle time, our analytic framework optimizes the degree of speculation for better performance. Our experiments on a Fujitsu AP3000 distributed-memory parallel computer simulating several applications show that the predicted performance metrics deviate from the measured values by less than 8%. Both the analytical and experimental results have ascertained that speculation without rollbacks may not produce the best elapsed time. Instead, a controlled degree of casuality error is preferred in most practical cases.

关键词： computer simulation

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