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检索条件"任意字段=Proceedings of the 34th Annual ACM/IEEE Symposium on Logic in Computer Science"

共 360 条记录，以下是211-220 订阅

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Reducing the complexity of the register file in dynamic superscalar processors

Reducing the complexity of the register file in dynamic supe...

引用

ieee/acm International symposium on Microarchitecture (MICRO)

作者： R. Balasubramonian S. Dwarkadas D.H. Albonesi Department of Computer Science University of Rochester USA Department of Electrical and Computer Engineering University of Rochester USA

Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. the number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register at dispatch. A large multi-ported register file helps improve the instruction-level parallelism (ILP), but may have a detrimental effect on clock speed, especially in future wire-limited technologies. In this paper, we propose a register file organization that reduces register file size and port requirements for a given amount of ILP. We use a two-level register file organization to reduce register file size requirements, and a banked organization to reduce port requirements. We demonstrate empirically that the resulting register file organizations have reduced latency and (in the case of the banked organization) energy requirements for similar instructions per cycle (IPC) performance and improved instructions per second (IPS) performance in comparison to a conventional monolithic register file. the choice of organization is dependent on design goals.

关键词： Registers Clocks Delay effects computer science Parallel processing Bandwidth Read-write memory Frequency Wire Multithreading

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Modulo scheduling with integrated register spilling for clustered VLIW architectures

Modulo scheduling with integrated register spilling for clus...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： J. Zalamea J. Llosa E. Ayguade M. Valero Department d' Arquitectura de Computadors (UPC) Universitat Poliltècnica de Catalunya Spain

Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are needed to move data between them. New aggressive instruction scheduling techniques are required to minimize the negative effect of resource clustering and delays in moving data around. In this paper we present a novel software pipelining technique that performs instruction scheduling with reduced register requirements, register allocation, register spilling and inter-cluster communication in a single step. the algorithm uses limited backtracking to reconsider previously taken decisions. this backtracking provides the algorithm with additional possibilities for obtaining high throughput schedules with low spill code requirements for clustered architectures. We show that the proposed approach outperforms previously proposed techniques and that it is very scalable independently of the number of clusters, the number of communication buses and communication latency. the paper also includes an exploration of some parameters in the design of future clustered VLIW cores.

关键词： VLIW Registers Processor scheduling Pipeline processing Energy consumption throughput computer architecture Scheduling algorithm logic Dynamic scheduling

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Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources

Reducing power requirements of instruction scheduling throug...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： D. Ponomarev G. Kucuk K. Ghose Department of Computer Science State University of New York Binghamton NY USA

the "one-size-fits-all" philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize performance across a wide range of applications results in the overcommitment of resources in general. To reduce power dissipation in the datapath, the resource allocations can be dynamically adjusted based on the demands of applications. We propose a mechanism to dynamically, simultaneously and independently adjust the sizes of the issue queue (IQ), the reorder buffer (ROB) and the load/store queue (LSQ) based on the periodic sampling of their occupancies to achieve significant power savings with minimal impact on performance. Resource upsizing is done more aggressively (compared to downsizing) using the relative rate of blocked dispatches to limit the performance penalty. Our results are validated by the execution of SPEC 95 benchmark suite on a substantially modified version of Simplescalar simulator, where the IQ, the ROB, the LSQ and the register files are implemented as separate structures, as is the case with most practical implementations. For the SPEC 95 benchmarks, the use of our technique in a 4-way superscalar processor results in a power savings in excess of 70% within individual components and an average power savings of 53% for the IQ, LSQ and ROB combined for the entire benchmark suite with an average performance penalty of only 5%.

关键词： Dynamic scheduling Resource management Power dissipation Processor scheduling computer science Application software Sampling methods Registers Energy efficiency Out of order

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Compiler-directed early load-address generation

Compiler-directed early load-address generation

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： Ben Chung Cheng D.A. Connors W.W. Hwu Department of Computer Science The Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical and Computer Engineering The Coordinated Science Laboratory University of Illinois Urbana IL USA

Two orthogonal hardware techniques, table-based address prediction and early address calculation, for reducing the latency of load instructions have been recently proposed. the key idea behind both of these techniques is to speculatively perform loads early in the processor pipeline using predicted values for the loads' addresses. these techniques have required either a large hardware table or complex register bypass logic to be implemented in order to accurately predict the important loads in the presence of a large number of less-important loads. this paper proposes a compiler directed approach that allows a streamlined version of both of these techniques to be effectively used together. the compiler provides directives to indicate which prediction mechanism to use or, when appropriate, that a prediction should not be made. the hardware therefore can be focused on their target cases so that a smaller prediction table and simpler bypass logic suffice. Our results show that through straightforward compiler heuristics, we obtain an average speedup of 34% with a 256-entry direct-mapped address table and only one cached register. And with the help of address profiling, an extra 4% of speedup can be obtained.

关键词： Delay Pipelines Hardware logic Microarchitecture computer science Registers Microprocessors computer architecture computer aided instruction

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Symbolic timing verification of timing diagrams using Presburger formulas 97

Symbolic timing verification of timing diagrams using Presbu...

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34th Design Automation Conference

作者： Amon, T Borriello, G Hu, TK Liu, JW Department of Computer Science Southwest Texas State University San Marcos TX Department of Computer Science and Engineering University of Washington Seattle WA

ISBN: (纸本)0897919203

We present a novel set of tools for performing symbolic timing verification of timing diagrams. the tools are multi-purpose with uses in verification, derivation of synthesis constraints, and design evaluation. Our methodology is based on using techniques for manipulating Presburger formulas. We demonstrate using several interesting examples that the method is efficient in practice and should be considered for inclusion in commercial tools.

关键词： computer aided logic design

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A comparison of data prefetching on an access decoupled and superscalar machine 30

A comparison of data prefetching on an access decoupled and ...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： G.P. Jones N.P. Topham Department of Computer Science Edinburgh University Edinburgh UK

ISBN: (纸本)9780818679773

We investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are benefits to using the decoupling paradigm given that an out-of-order (o-o-o) superscalar architecture could in principle prefetch to the same degree as an access decoupled machine. We have found that for large issue width the access decoupled machine can hide memory latency more effectively than a single instruction window o-o-o superscalar architecture. Our findings also demonstrate that an access decoupled machine offers the benefit of reducing the complexity of window issue logic.

关键词： Prefetching Delay Arithmetic computer science Parallel processing computer architecture logic design Microprocessors Costs Clocks

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Architectural exploration using Verilog-based power estimation: a case study of the IDCT 97

Architectural exploration using Verilog-based power estimati...

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proceedings of the 34th annual Design Automation Conference

作者： thucydides Xanthopoulos Yoshifumi Yaoi Anantha Chandrakasan Department of Electrical Engineeering and Computer Science Massachusetts Institute of Technology Cambridge

ISBN: (纸本)9780897919203

We describe an architectural design space exploration methodologythat minimizes the energy dissipation of digital *** centerpiece of our methodology is a Verilog-based power estimationtool, Pythia, that blends the accuracy of low-level circuitsimulators such as powermill with the speed of high level powerestimators geared to design exploration. Pythia takes into accountvoltage-dependent capacitive nonlinearities and supports runtimeadaptation of supply voltage. It employs a hybrid modelingaproach in which low-level simulation of logic gates and flip-flopscan be combined with high level macromodels for memory structureswhere the energy per access is not as sensitive to input datastatistics. the speed and accuracy of Pythia has enabled a detailedcase study of two different approaches for the computation of theInverse Discrete Cosine Transform, an integral component of theMPEG video coding algorithm. One approach uses conventionalmethods and the other exploits signal statistics to dynamically minimizethe average number of operations required and the operatingsupply voltage.

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Microarchitecture support for improving the performance of load target prediction 30

Microarchitecture support for improving the performance of l...

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ieee/acm International symposium on Microarchitecture (MICRO)

作者： Chung-Ho Chen A. Wu Department of Electronic Engineering National Yunlin University of Science and Technology Yunlin Taiwan

ISBN: (纸本)9780818679773

Presents a load target prediction scheme that mitigates the impact of load latency for modern microprocessors. the scheme uses a cache-like buffer to provide the base address, offset and operand size at the instruction fetching stage of a pipeline so that a load target address can be computed earlier at the decode stage. With the dynamic use of a load stride, the scheme has achieved a prediction rate that is 15% higher than a previously proposed approach. By providing a 128-entry direct-mapped load-prediction buffer, two adders and two forwarding paths, for a 4-fetch processor the scheme provides an average speedup of 10% to 32% in performance improvement as the data cache latency increases from 2 cycles to 4 cycles. A bit-array design that supports multiple-cast writes and eliminates the associative logic commonly used in base register caching is developed for the prediction scheme.

关键词： Microarchitecture Delay Pipelines computer aided instruction Clocks Registers logic design Design optimization Prefetching Processor scheduling

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A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications 97

A real-time RTL engineering-change method supporting on-line...

引用

proceedings of the 34th annual Design Automation Conference

作者： Wen-Jong Fang Allen C.-H. Wu Ti-Yen Yen Department of Computer Science Tsing Hua University Hsinchu Taiwan 300 Republic of China Quickturn Design Systems Inc. 440 Clyde Avenue Mountain View California

ISBN: (纸本)9780897919203

In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues to engineeringchanges is the turn-around time. Ideally, after designers modify their designs, they resume their debugging and verification tasks immediately. However, converting a design from its Register-Transfer-Level (RTL) description to a target emulator is a time-consuming procedure which may take hours. Such long engineering-change turn-around times are unacceptable by the designers. In this paper, we present a real-time RTLengineering-change method supporting on-line debuggingfor logic-emulation applications. We propose a novel design method which is able to link design data generated at different design stages in a unified way. Using thismethod, the users can immediately locate the portion ofthe circuit design affected by the design modification fromits RTL specification. this feature provides users with afast time-to-debug environment by significantly improving the efficiency of the engineering-change process. We have developed aprototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the effectiveness of the proposed method.

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Linear logic, monads and the lambda calculus

Linear logic, monads and the lambda calculus

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11th annual ieee symposium on logic in computer science (LIVS 96)

作者： Benton, N Wadler, P UNIV CAMBRIDGE COMP LABCAMBRIDGE CB2 3QGENGLAND

ISBN: (纸本)0780336542

Models of intuitionistic linear logic also provide models of Moggi's computational metalanguage. We use the adjoint presentation of these models and the associated adjoint calculus to show that three translations, due mainly to Moggi, of the lambda calculus into the computational metalanguage (direct, call-by-name and call-by-value) correspond exactly to three translations, due mainly to Girard, of intuitionistic logic into intuitionistic linear logic. We also consider extending these results to languages with recursion.

关键词： Formal logic

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