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Design and implementation of high performance architectures with partially reconfigurable CGRAs

Design and implementation of high performance architectures ...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Moghaddam, Mansureh Shahraki Paul, Kolin Balakrishnan, M. Department of Computer Science and Engineering IIT Delhi Delhi India

ISBN: (纸本)9780769549798

Programmable hardware built on a regular architecture can be used to address the challenges associated with using many fixed core architectures for applications which have varying compute power requirements during the lifetime of execution. the fine granularity of FPGAs is however unsuitable for effectively exploiting runtime reconfiguration because of the high overheads involved. Effective use of a dynamically reconfigurable fabric across a range of applications remains a challenge. In this work, we use a model coarse grain reconfigurable fabric to explore the potential of such a fabric for a range of key reconfiguration parameters. this coarse grain reconfigurable array with malleable communication links is used for design space exploration of two compute intensive kernel implementations which exploit dynamically reconfiguration. the semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each epoch of computation. Different blocks of the application program reuse the compute grain in different epochs. Some of the links between the compute tiles are changed during the reconfiguration phase and because the architecture is partially reconfigured, the reconfiguration in some tiles can be completely overlapped with computation in other tiles. the paper proposes a methodology to exploit this design paradigm to drastically reduce the context switch overhead for rebalancing the pipeline to build high performance/area applications on this fabric. © 2013 ieee.

关键词： Dynamic models

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Investigating the feasibility of making contexts explicit in designing cloud workflow

Investigating the feasibility of making contexts explicit in...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Fan, Xiaoliang Zhang, Ruisheng Brezillon, Patrick School of Information Science and Engineering Lanzhou University Lanzhou Gansu China Laboratory of Computer Sciences of Paris 6 University Pierre and Marie CURIE Paris France

ISBN: (纸本)9780769549798

Cloud workflow allows automating the workflow process through a compilation of known sequences of actions in cloud environment. Current Cloud workflows lack the ability, in the one hand, to capture the contexts during the design phase of Cloud workflows;and in the other hand, to deliver a real-time assistance to help a specific user interact with the system in the selection of the relevant cloud workflow components for his specific need. We propose a context-oriented approach to improve the design phase of cloud workflows. A user-oriented paradigm is presented to make contexts explicit in designing cloud workflows. Context will be made explicit due to the integration of BPEL and Contextual Graphs (CxGs) representation. CxGs representation is the formalism for representing uniformly all the ingredients of design process in cloud workflows, so that users could customize information, formalize their design strategies, and possibly interact with the system to model the cloud workflow. We illustrate our methodology through a case study in virtual screening to testify our investigation study. Finally, we conclude that the method we proposed for making contexts explicit in Cloud workflows could be considered as a successful attempt to address the social and human factors related to the design of Cloud workflows. © 2013 ieee.

关键词： Design

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TSHMEM: Shared-memory parallel computing on tilera many-core processors

TSHMEM: Shared-memory parallel computing on tilera many-core...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Lam, Bryant C. George, Alan D. Lam, Herman NSF Center for High-Performance Reconfigurable Computing Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611-6200 United States

ISBN: (纸本)9780769549798

With many-core processor architectures emerging, concerns arise regarding the productivity of numerous parallel programming tools, models, and languages as developers from a broad spectrum of science domains struggle to maximize performance and maintain correctness of their applications. Fortunately, a partitioned global address space (PGAS) programming model has demonstrated realizable performance and productivity potential for large parallel computing systems with distributed-memory architectures. One such PGAS approach is SHMEM, a lightweight, shared-memory programming library. Renewed interest for SHMEM has developed around Oppenheim, a recent community-led effort to produce a standardized specification for the SHMEM library amidst incompatible commercial implementations. this paper presents and evaluates the design of TSHMEM (short for TileSHMEM), a new OpenSHMEM library for the Tilera TILE-Gx8036 and TILEPro64 many-core processors. TSHMEM is built atop Tilera-provided libraries with key emphasis upon realizable performance with those libraries, demonstrated through micro benchmarking. Furthermore, SHMEM application portability is illustrated with two case studies. TSHMEM successfully delivers high performance with ease of programmability and portability for SHMEM applications on TILE-Gx and TILEPro architectures. © 2013 ieee.

关键词： Parallel programming

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Symmetric comparison-based fault diagnosis of multiprocessor and distributed systems using nonlinear support vector machines

Symmetric comparison-based fault diagnosis of multiprocessor...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Elhadef, Mourad College of Engineering and Computer Science Abu-Dhabi University PO.Box 59911 Abu-Dhabi United Arab Emirates

ISBN: (纸本)9780769549798

In this paper, the problem of identifying the set of permanent faulty nodes using partial syndromes, i.e., when not all the comparison outcomes are available prior to initiating the diagnosis phase, is considered. A new diagnosis approach, using nonlinear support vector machines (SVMs), is described. We consider the symmetric comparison diagnosis model which assumes that nodes are assigned a set of tasks and their outcomes are compared, and that at most t nodes can fail simultaneously. Based on the agreements and disagreements among the nodes' outputs, the diagnosis algorithm must identify all faulty nodes. the new nonlinear SVM-based fault identification algorithm is first trained using various syndromes with known fault sets. then, it is extensively tested using randomly generated diagnosable systems of different sizes and under various fault scenarios. Simulations showed that the nonlinear SVM-based diagnosis performed efficiently, i.e. the diagnosis algorithm correctly identified almost all the faulty nodes even when at most half of the comparison outcomes are missing. In addition, results from the thorough simulation study demonstrate the effectiveness of the nonlinear SVM-based fault identification algorithm, in terms of diagnosis correctness, latency, and scalability. © 2013 ieee.

关键词： Fault tolerance

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EasyHPS: A multilevel hybrid parallel system for dynamic programming

EasyHPS: A multilevel hybrid parallel system for dynamic pro...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Du, Jun Yu, Ce Sun, Jizhou Sun, Chao Tang, Shanjiang Yin, Yanlong School of Computer Science and Technology Tianjin University China School of Computer Engineering Nanyang Technological University Singapore Department of Computer Science Illinois Institute of Technology Chicago IL 60616 United States

ISBN: (纸本)9780769549798

Dynamic programming approach solves complex problems efficiently by breaking them down into simpler sub-problems, and is widely utilized in scientific computing. With the increasing data volume of scientific applications and development of multi-core/multi-processor hardware technologies, it is necessary to develop efficient techniques for parallelizing dynamic programming algorithms, particularly in multilevel computing environment. the intrinsically strong data dependency of dynamic programming also makes it difficult and error-prone for the programmer to write a correct and efficient parallel program. In order to make the parallel programming easier and more efficient, we have developed a multilevel hybrid parallel runtime system for dynamic programming named EasyHPS based on the Directed Acyclic Graph(DAG) Data Driven Model in this paper. the EasyHPS system encapsulates details of parallelization implementation, such as task scheduling and message passing, and provides easy API for users to reduce the complexity of parallel programming parallelization. In the DAG Data Driven Model, the entire application is initially partitioned by data partitioning into sub-tasks that each sub-task processing a data block. then all sub-tasks are modeled as a DAG, in which each vertex represents a sub-task and each edge indicates the communication dependency between the two sub-tasks. In task scheduling, a dynamic approach is proposed based on DAG Data Driven Model to achieve load balancing. Data partitioning and task scheduling are both done on processor-level and thread-level in the multilevel computing environment. In addition, experimental results demonstrate that the proposed dynamic scheduling approach in EasyHPS is more efficient in comparison with those static ones such as block-cyclic based wave front. © 2013 ieee.

关键词： Directed graphs

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Acceleration of a high order finite-difference WENO scheme for large-scale cosmological simulations on GPU

Acceleration of a high order finite-difference WENO scheme f...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Meng, Chen Wang, Long Cao, Zongyan Ye, Xianfeng Feng, Long-Long Supercomputing Center Computer Network Information Center Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China National Astronomical Observatories Chinese Academy of Sciences Beijing China Purple Mountain Observatory Chinese Academy of Sciences Beijing China Center for Astrophysics University of Science and Technology of China Anhui China

ISBN: (纸本)9780769549798

In this work, we present our implementation of a three-dimensional 5th order finite-difference weighted essentially non-oscillatory (WENO) scheme in double precision on CPU/GPU clusters, which targets on large-scale cosmological hydrodynamic flow simulations involving both shocks and complicated smooth solution structures. In the level of MPI parallelization, we subdivided the domain along each of three axial directions. then on each process, we ported the WENO computation to GPU. this method is memory-bound derived from the calculations of the weights and it becomes a greater challenge for a 3D high order problem in double precision. To make full use of impressive computing power of GPU and avoid its memory limitation, we performed a series of optimizations that are focused on memory accessing mode at all levels. We subjected this code to a number of typical tests for the evaluation of effectiveness and efficiency. Our tests indicate that, in a mono-thread Fortran code reference, the GPU version achieves a 12~19 speed-up and about 19~36 in the computation part. We analyzed the results on both Fermi and Kepler GPUs. We also outlined what is needed to further increase the speed by reducing the time spent on the communications part and other future work. © 2013 ieee.

关键词： Graphics processing unit

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Parallel macro pipelining on the intel SCC many-core computer

Parallel macro pipelining on the intel SCC many-core compute...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Suss, Tim Schoenrock, Andrew Meisner, Sebastian Plessl, Christian Johannes Gutenberg-University Mainz Zentrum fur Datenverarbeitung Mainz Germany Carleton University School of Computer Science Ottawa Canada University of Paderborn Paderborn Center for Parallel Computing Paderborn Germany

ISBN: (纸本)9780769549798

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on the SCC. We show that we can further improve performance by using SCC's controlling PC in conjunction with the SCC. We also identify aspects of the SCC that hinder the overall performance, mainly the lack of local memory banks for each core on the SCC. the results presented in this paper are not limited to only image processing, but users could expect similar experiences where macro pipelining is used in other applications on the SCC. © 2013 ieee.

关键词： Pipelines

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Operation synchronization technique on pipeline-based hardware synthesis applying stream-based computing framework

Operation synchronization technique on pipeline-based hardwa...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Yamagiwa, Shinichi Watanabe, Ryoyu Wada, Koichi Faculty of Engineering Information and Systems Dept. of Computet Science University of Tsukuba 1-1-1 Tennodai Tsukuba Ibaraki Japan

ISBN: (纸本)9780769549798

Increasing the needs for real-time processing of information flood from environment surrounded us acquired by the advanced sensing technologies, any application acquiring such information requires a processing ability for large input dataflow that must be processed within a restricted short time. In order to achieve the required processing performance, we often consider pipeline-based hardware implementation. the timing for activating operators for input data in the design must be scheduled carefully arranging the timings for I/O among operators. However, when we need to revise the algorithm itself or any parameters, it is very hard to reschedule the activation timings of operators considering the design goals regarding the maximum frequency and the resource size. this paper shows a technique to schedule operation timings synchronizing the input data in a processing pipeline of hardware applying the stream-based computing framework using OpenCL kernel description. this paper especially proposes a new compiler-based approach for synthesizing the pipeline-based hardware applying a novel technique for calculating the timings at the operators' activation called the Pipeline Timing Adjustment (PTA). this paper mainly discusses the algorithm of the PTA and show the effect of the algorithm. © 2013 ieee.

关键词： Pipelines

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Exploring programming multi-GPUs using OpenMP and OpenACC-based hybrid model

Exploring programming multi-GPUs using OpenMP and OpenACC-ba...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Xu, Rengan Chandrasekaran, Sunita Chapman, Barbara Dept. of Computer Science University of Houston Houston United States

ISBN: (纸本)9780769549798

Heterogeneous computing come with tremendous potential and is a leading candidate for scientific applications that are becoming more and more complex. Accelerators such as GPUs whose computing momentum is growing faster than ever offer application performance when compute intensive portions of an application are offloaded to them. It is quite evident that future computing architectures are moving towards hybrid systems consisting of multi-GPUs and multi-core CPUs. A variety of high-level languages and software tools can simplify programming these systems. Directive-based programming models are being embraced since they not only ease programming complex systems but also abstract low-level details from the programmer. We already know that OpenMP has been making programming CPUs easy and portable. Similarly, a directive-based programming model for accelerators is OpenACC that is gaining popularity since the directives play an important role in developing portable software for GPUs. A combination of OpenMP and OpenACC, a hybrid model, is a plausible solution to port scientific applications to heterogeneous architectures especially when there is more than one GPU on a single node to port an application to. However OpenACC meant for accelerators is yet to provide support for multi-GPUs. But using OpenMP we could conveniently exploit features such as for and section to distribute compute intensive kernels to more than one GPU. We demonstrate the effectiveness of this hybrid approach with some case studies in this paper. © 2013 ieee.

关键词： Program processors

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A flexible memory controller supporting deep belief networks with fixed-point arithmetic

A flexible memory controller supporting deep belief networks...

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2013 ieee 37th annual computer Software and Applications Conference, COMPSAC 2013

作者： Jiang, Jingfei Hu, Rongdong Lujan, Mikel School of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769549798

Deep Belief Networks (DBNs) are state-of-Art Machine Learning techniques and one of the most important unsupervised learning algorithms. Training DBNs is computationally intensive which naturally leads to investigate FPGA acceleration. Fixed-point arithmetic can have an important influence on the execution time and prediction accuracy of a DBN. Previous studies have focused only on customized DBN accelerators with a fixed data-width. Our results experiments demonstrate that supporting various data-widths in different DBN configurations and application environments does make sense for achieving acceptable performance. From this we conclude that a DBN accelerator should support various data-widths rather than the fixed one as done in previous work. the processing performance of DBN accelerators in FPGA is almost always constrained not by the capacity of the processing units, but by their on-chip RAM capacity and speed. We propose an efficient memory controller for DBN accelerators, which shows that supporting various data-widths is not as difficult as it may sound. the cost is only little in hardware terms and does not affect the critical path. We have designed a tool to help users reconfiguring the memory controller with arbitrary data-width flexibly. © 2013 ieee.

关键词： Field programmable gate arrays (FPGA)

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