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Implemented parallel Annealing in Scalable Fully Coupled Annealing processing System 20

Implemented Parallel Annealing in Scalable Fully Coupled Ann...

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20th ieee Jubilee World symposium on Applied Machine Intelligence and Informatics, SAMI 2022

作者： Yamamoto, Kaoru Kawahara, Takayuki Tokyo University of Science Department of Electrical Engineering Tokyo Japan

ISBN: (纸本)9781665497046

there has been progress in annealing processors for solving combinatorial optimization problems. there are two types of annealing processors: the "sparsely coupled"type, which implements only some spin-to-spin couplings, and the "fully coupled"type, which implements all spin-to-spin couplings. the latter has the advantage of having a large number of problems to be solved per spin, but had been said to have the disadvantage of poor scalability due to the complicated coupling. To overcome this, we first created a scalable Fully coupled annealing processing system (SFCAPS) by using multi-chip operation and implemented it on an FPGA board. this is to reduce the amount of coupling per chip by performing the multi-chip operation, and to improve the scalability by facilitating the connection between the chips. However, in the architecture, multi-chip operation could not be fully used and most of the chips on the board were idle for a large amount of time. therefore, for this study, we implemented a parallel annealing method called multi-spin threading on this architecture to reduce the number of idle chips and demonstrated that the architecture can operate more efficiently. As a result, the architecture became more efficient, which raised the parallelism of the architecture. this has resulted in an average 5% improvement in the accuracy of the annealing processor's solution, demonstrating that it is easier to achieve a high accuracy solution. © 2022 ieee.

关键词： Couplings Annealing Scalability Instruction sets Pipelines parallel processing Informatics

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SR2C: A Structurally Redundant Short Reads Collapser for Optimizing DNA Data Compression 29

SR2C: A Structurally Redundant Short Reads Collapser for Opt...

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29th ieee International Conference on parallel and distributed Systems, ICPADS 2023

作者： Sun, Hui Ma, Huidong Zheng, Yingfeng Xie, Haonan Wang, Xiaofei Liu, Xiaoguang Wang, Gang Nankai University College of C.S. Nankai-Orange D.T. Joint Lab Nankai-Baidu Joint Lab ICIC TMCC SysNet DISSec GTIISC Tianjin300350 China Guangxi University School of Electrical Engineering Nanning530004 China

ISBN: (纸本)9798350330717

the current redundant sequence deduplication algorithms cannot remove structural repetitive DNA short reads such as mirror, reverse, paired, and complementary palindromes in high-throughput genomics sequencing data. Moreover, these methods also cannot construct indexes to recover the original sequences, thus failing to meet the requirements of lossless compression for downstream applications. To address these problems, we propose a data structure called Cycle-Hash-Linkage (CHL) and present a CPU parallelism optimization algorithm named SR2C (Structurally Redundant Short Reads Collapser) based on CHL to improve the compression ratio of DNA sequencing data. Experimental results on actual data from the NCBI database demonstrate that SR2C achieves an average residual sequence percentage improvement of 2.556% compared to the state-of-the-art redundant sequence deduplication algorithm, Minirmd. Furthermore, SR2C cascaded optimization improves the average compression ratios of compression algorithms Pigz, PBzip2, XZ, and 7Z by 92.345%, 78.999%, 10.132%, and 7.434%, respectively. By leveraging multi-core CPU parallel computation, SR2C effectively reduces time consumption, which achieves 2-5X deduplication and recovers *** same name Linux toolkit is freely available at https://***/fahaihi/SR2C. © 2023 ieee.

关键词： data compression DNA sequencing data compression parallel algorithm redundancy deduplication rolling-hash algorithm structurally redundant reads

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Grouping Synchronous to Eliminate Stragglers with Edge Computing in distributed Deep Learning 19

Grouping Synchronous to Eliminate Stragglers with Edge Compu...

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19th ieee International symposium on parallel and distributed processing with Applications (ieee ISPA)

作者： Gui, Zhiyi Yang, Xiang Yang, Hao Li, Wei Zhang, Lei Qi, Qi Wang, Jingyu Sun, Haifeng Liao, Jianxin Beijing Univ Posts & Telecommun State Key Lab Networking & Switching Technol Beijing Peoples R China Huawei Beijing Peoples R China

ISBN: (纸本)9781665435741

With the development of artificial intelligence(AI) applications, a large number of data are generated from mobile or IoT devices at the edge of the network. Deep learning tasks are executed to obtain effective information in the user data. However, the edge nodes are heterogeneous and the network bandwidth is limited in this case, which will cause general distributed deep learning to be inefficient. In this paper, we propose Group Synchronous parallel (GSP), which uses a density-based algorithm to group edge nodes with similar training speeds together. In order to eliminate stragglers, group parameter servers are responsible for coordinating communication of nodes in the group with Stale Synchronous parallel and aggregating the gradients of these nodes. And a global parameter server is responsible for aggregating the gradients from the group parameter servers to update the global model. To save network bandwidth, we further propose Grouping Dynamic Sparsification (GDS). It adjusts the gradient sparsification rate of nodes dynamically based on GSP so as to differentiates the communication volume and makes the training speed of all nodes tend to be the same. We evaluate GSP and GDS's performance on LeNet-5, ResNet, VGG, and Seq2Seq with Attention. the experimental results show that GSP speedups the training by 45% similar to 120% with 16 nodes. GDS on top of GSP can make up for some test accuracy loss, up to 0.82% for LeNet-5.

关键词： distributed deep training gradient compression parameter server gradient sparsification

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Base Station handover Based on User Trajectory Prediction in 5G Networks 19

Base Station handover Based on User Trajectory Prediction in...

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19th ieee International symposium on parallel and distributed processing with Applications (ieee ISPA)

作者： Ma, Yuxiang Chen, Xuefei Zhang, Lei Henan Univ Sch Comp & Informat Engn Kaifeng 475004 Peoples R China Henan Univ Henan Key Lab Big Data Anal & Proc Kaifeng 475004 Peoples R China

ISBN: (纸本)9781665435741

In the 5G era, user equipment connected to 5G base stations can obtain better communication services. However, due to the limited coverage of base stations, the movement of users may cause frequent handover of base stations. With the widespread deployment of 5G base stations, how to reduce unnecessary handover times when users connect to the base station becomes particularly important. In recent years, user trajectory data has been mined and applied to many scenarios. In the 5G network, by judging the user's movement trajectory, the number of handovers required for the user to connect to the 5G base station can be effectively reduced. In this paper, we propose a 5G base station handover method based on trajectory prediction. A CNN-LSTM neural network, which combines a Convolutional Neural Network (CNN) and Long Short-Term Memory (LSTM) has been proposed to predict the user's trajectory. the evaluation results show that our mechanism can effectively reduce the number of base station handovers and improve the efficiency of users using the network. In addition, the stability of 5G networks can be improved by reducing inefficient base station handover.

关键词： 5G network base station handover trajectory prediction

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BiPS: Hotness-aware Bi-tier Parameter Synchronization for Recommendation Models 35

BiPS: Hotness-aware Bi-tier Parameter Synchronization for Re...

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35th ieee International parallel and distributed processing symposium (IPDPS)

作者： Zheng, Qiming Chen, Quan Bai, Kaihao Guo, Huifeng Gao, Yong He, Xiuqiang Guo, Minyi Shanghai Jiao Tong Univ Shanghai Peoples R China Huawei Technol Ltd Shenzhen Peoples R China

ISBN: (纸本)9781665440660

While current deep learning frameworks are mainly optimized for dense-accessed models, they show low throughput and poor scalability in training sparse-accessed recommendation models. Our investigation shows that the poor performance is due to the parameter synchronization bottleneck. We therefore propose BiPS, a bi-tier parameter synchronization system that alleviates the parameter update and the sparse-accessed parameters communication bottleneck. BiPS includes a bi-tier parameter server that accelerates the traditional CPU-based parameter update process, a hotness-aware parameter placement and communication policy to balance the workloads between CPU and GPU and optimize the communication of sparse-accessed parameters. BiPS overlaps the worker computation with the synchronization stage to enable parameter updates in advance. We implement BiPS and incorporate it into mainstream DL frameworks including TensorFlow, MXNet, and PyTorch. the experimental results based on various deep learning frameworks show that BiPS greatly speeds up the training of recommenders (5 - 9 x) as the model scale increases, without degrading the accuracy.

关键词： Training Deep learning distributed processing Scalability Graphics processing units Computer architecture throughput

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Centralized Graph based TSCH Scheduling for IoT Network Applications 19

Centralized Graph based TSCH Scheduling for IoT Network Appl...

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19th ieee International symposium on parallel and distributed processing with Applications (ieee ISPA)

作者： Choudhury, Nikumani Nasralla, Moustafa M. Gupta, Prakhar Rehman, Ikram Ur Birla Inst Technol & Sci Dept Comp Sci & Informat Syst Hyderabad India Prince Sultan Univ Dept Commun & Networks Engn Riyadh Saudi Arabia Univ West London Sch Comp & Engn London W5 5RF England

ISBN: (纸本)9781665435741

the current specification of the ieee 802.15.4 standard supports several application specific Quality of Service (QoS) requirements for Internet of things (IoT) network applications. Specifically, the Time Slotted Channel Hopping (TSCH) MAC mode provides effective latency and throughput performance through the use of dedicated timeslots between two communicating devices. Despite the impact TSCH MAC can facilitate in low-power lossy networks (LLNs), the standard does not explore either the building or maintaining of a schedule. the challenge is to build an energy-efficient TSCH schedule that repeats periodically over several channels. To address this problem, we propose a centralized cluster-level TSCH scheduling mechanism from the energy-efficiency perspective. the proposed mechanism derives a collision graph for each of the clusters in the network topology to schedule non-overlapping timeslots. the Bron-Kerbosch algorithm is used as a sub-procedure for finding the complete sub-graphs of a graph. In addition, we analytically compute the transmission and energy overhead with the help of a Markov Model for TSCH.

关键词： ieee 802.15.4 Internet of things TSCH MAC scheduling Bron-Kerbosch Algorithm

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distributed Training of Embeddings using Graph Analytics 35

Distributed Training of Embeddings using Graph Analytics

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35th ieee International parallel and distributed processing symposium (IPDPS)

作者： Gill, Gurbinder Dathathri, Roshan Maleki, Saeed Musuvathi, Madan Mytkowicz, Todd Saarikivi, Olli Katana Graph Inc Austin TX 78705 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781665440660

Many applications today, such as natural language processing, network and code analysis, rely on semantically embedding objects into low-dimensional fixed-length vectors. Such embeddings naturally provide a way to perform useful downstream tasks, such as identifying relations among objects and predicting objects for a given context. Unfortunately, training accurate embeddings is usually computationally intensive and requires processing large amounts of data. this paper presents a distributed training framework for a class of applications that use Skip gram like models to generate embeddings. We call this class Any2Vec and it includes Word2Vec (Gensim), and Vertex2Vec (DeepWalk and Node2Vec) among others. We first formulate Any2Vec training algorithm as a graph application. We then adapt the state-of-the-art distributed graph analytics framework, D-Galois, to support dynamic graph generation and re-partitioning, and incorporate novel communication optimizations. We show that on a cluster of 32 48-core hosts our framework GraphAny2Vec matches the accuracy of the state-of-the-art shared-memory implementations of Word2Vec and Vertex2Vec, and gives geo-mean speedups of 12 x and 5x respectively. Furthermore, GraphAny2Vec is on average 2x faster than DMTK, the state-of-the-art distributed Word2Vec implementation, on 32 hosts while yielding much better accuracy.

关键词： Machine Learning Graph Analytics distributed Computing

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GraphBLAS: C++ Iterators for Sparse Matrices 36

GraphBLAS: C++ Iterators for Sparse Matrices

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36th ieee International parallel and distributed processing symposium Workshops, IPDPSW 2022

作者： Brock, Benjamin McMillan, Scott Buluc, Aydin Mattson, Timothy G. Moreira, Jose E. University of California Eecs Department BerkeleyCA United States Software Engineering Institute Carnegie Mellon University PittsburghPA United States Lawrence Berkeley National Laboratory Computational Research Department BerkeleyCA United States Parallel Computing Lab Intel Ocean ParkWA United States Ibm Thomas J. Watson Research Center Yorktown HeightsNY United States

ISBN: (纸本)9781665497473

Iteration over opaque, generic data structures is an important feature of many C++ libraries. Aggressive compiler optimization and inlining enables generic C++ iterators to iterate over complex data structures with performance comparable to that of hand-tuned code with C-language (raw) pointers. In this paper, we describe the sparse matrix iterators in the current draft of the C++ GraphBLAS API, their support for a variety of backend data formats, and implementation strategies we have considered. We compare performance of these iterators to that of hand-tuned iteration with raw pointers, showing that our iterators introduce minimal overhead. We consider extensions to our iterator design for interoperability with the draft C++ Graph Library proposal and to support different semantics for iterating over sparse matrices (by row, by column, by specific diagonals, etc.). © 2022 ieee.

关键词： Semantics

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Implementation of Self-Organizing Map with Content Addressable Memory-based Massive-parallel SIMD Matrix processing Core 5

Implementation of Self-Organizing Map with Content Addressab...

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5th World symposium on Communication Engineering, WSCE 2022

作者： Hamano, Hajime Arai, Sota Hamai, Akimitsu Kageyama, Kyosuke Xiangbo, Kong Koide, Tetsushi Kumaki, Takeshi Ritsumeikan University Faculty of Science and Engineering Ritsumeikan University 1-1-1 Noji-Higashi Kusatsu Shiga Kusatsu Japan Electronic and Communication Engineering Kindai Univ Dept. of Electrical Osaka Japan Hiroshima University 1-4-2 Kagamiyama Hiroshima Higashi-Hiroshima739-8527 Japan

ISBN: (数字)9781665450577

ISBN: (纸本)9781665450577

Recently, several multimedia applications, such as digital image compression, digital video compression, and digital audio processing, are being executed on embedded devices. then, processing cores in such embedded devices are required to have high performance and programmability. In general, multimedia applications and machine learning algorithms consist of repeated arithmetic or logic operations and table-lookup coding operations. In order to improve the processing speed of these two operations, a CAMX (Content Addressable Memory-based massive-parallel SIMD matriX core) has been proposed. the role of the CAMX is to be an accelerator for a CPU core. the CAMX has several processing elements for highly parallel processing capability and consists of two CAM modules for fast table-lookup processing. In this paper, we have implemented the self-organizing map algorithm and compared it with Raspberry Pi. the CAMX is about 2.6 times faster than an Arm processor with NEON at the same frequency. In addition, the CAMX can reduce its operating frequency to one-third, if the CAMX and Arm processor with NEON run at the same processing speed. © 2022 ieee.

关键词： Table lookup

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indexPDT: A High Scalable distributed Classification Approach with Novel Cache Structure for Geo-location 25

indexPDT: A High Scalable Distributed Classification Approac...

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25th ieee International Conferences on High Performance Computing and Communications, 9th International Conference on Data Science and Systems, 21st ieee International Conference on Smart City and 9th ieee International Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Sun, Zhijie Li, Jing Xie, Jun Zheng, Binfan Zeng, Li Zhao, Rongqian Huawei Technologies Co. Ltd. Shenzhen China

ISBN: (纸本)9798350330014

Geo-location, also known as measurement report (MR) location, is a technique to determine the geographic location of user equipment (UE) and the behaviour attribute of telephone traffic based on wireless signals measured by the mobile communication network. the geographic location information can help to support network performance monitoring and evaluation. Considering accuracy and cost, we mainly adopt a hybrid location scheme combined with feature matching location and Weighted Centroid Correction Location (WCCL). As for feature matching location, over 20 billion samples gathered from tens of thousands of cells daily updated. Due to the vast data scale, feature analysis encounters a severe performance bottleneck. To address this problem, we design the indexed parallel decision tree (indexPDT) operator and integrate it into WindTensor, a self-innovated distributed machine learning (ML) engine. indexPDT is a classifier unit of the random forest (RF) algorithm with a novel cache structure. It performs structured cache processing on the dataset's meta-information, which can accompany the splitting of nodes. the cache structure can be quickly converted into statistical information to help find the optimal splitting point, effectively reducing memory usage and improving performance. Under the public datasets testing on 5 nodes, the mean speedup ratios are 86x and 3x compared with SparkML and XGBoost, respectively. In the Geo-location scenario, for a single cell, the speedup ratios are 82x and 4x compared with SparkML and XG Boost, respectively. © 2023 ieee.

关键词： Location

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