In this paper, we examine the problem of minimizing the variance of the download time in a particular Video on Demand System. this VOD system is based on a Grid Delivery Network which is an hybrid architecture based o...
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Graphics processing units (GPUs) originally designed for computer video cards have emerged as the most powerful chip in a high-performance workstation. Unlike multicore CPU architectures, which currently ship with two...
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Graphics processing units (GPUs) originally designed for computer video cards have emerged as the most powerful chip in a high-performance workstation. Unlike multicore CPU architectures, which currently ship with two or four cores, GPU architectures are "manycore" with hundreds of cores capable of running thousands of threads in parallel. NVIDIA's CUDA is a co-evolved hardware-software architecture that enables high-performance computing developers to harness the tremendous computational power and memory bandwidth of the GPU in a familiar programming environment - the C programming language. We describe the CUDA programming model and motivate its use in the biomedical imaging community.
the proceedings contain 86 papers. the topics discussed include: self-stabilizing distributed algorithms for networks;feature extraction and coverage problems in distributed sensor networks;a self-stabilizing algorith...
ISBN:
(纸本)3540747419
the proceedings contain 86 papers. the topics discussed include: self-stabilizing distributed algorithms for networks;feature extraction and coverage problems in distributed sensor networks;a self-stabilizing algorithm for 3-edge-connectivity;architecture-based optimization for mapping scientific applications to imagine;implementation and optimization of sparse matrix-vector multiplication on imagine stream processor;a mutual exclusion algorithm for mobile agents-based applications;a distributed metaheuristic for solving a real-world scheduling-routing-loading problem;key-attributes based optimistic data consistency maintenance method;parallelization strategies for the points of interests algorithm on the cell processor;and RWA algorithm for scheduled lightpath demands in WDM networks.
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWERS processor, a two-context simultaneous- multith...
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Testing large-scale distributed systems is a challenge, because some errors manifest themselves only after a distributed sequence of events that involves machine and network failures. D3S is a checker that allows deve...
Testing large-scale distributed systems is a challenge, because some errors manifest themselves only after a distributed sequence of events that involves machine and network failures. D3S is a checker that allows developers to specify predicates on distributed properties of a deployed system, and that checks these predicates while the system is running. When D3S finds a problem it produces the sequence of state changes that led to the problem, allowing developers to quickly find the root *** write predicates in a simple and sequential programming style, while D3S checks these predicates in a distributed and parallel manner to allow checking to be scalable to large systems and fault tolerant. By using binary instrumentation, D3S works transparently with legacy systems and can change predicates to be checked at runtime. An evaluation with 5 deployed systems shows that D3S can detect non-trivial correctness and performance bugs at runtime and with low performance overhead (less than 8%).
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