this paper presents the implementation of the EM-4 prototype and reports initial performance evaluation. the EM-4 is a highly parallel computer whose design objectives are: to develop a feasible parallel computer with...
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Sublinear parallel graph matching algorithms are investigated. the author proposes an approximation scheme for the cardinality matching problem on general graphs that runs in O(k5/logsup 4/n) parallel time using O(2k/...
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Mixed-mode parallel processors can quickly switch from executing instructions in Single Instruction, Multiple Data stream (SIMD) mode to executing them in Multiple Instruction, Multiple Data stream (MIMD) mode. To ful...
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In this paper we introduce the Orthogonalised Backpropagation Algorithm (OBA), a training procedure for adjusting the weights of a neural-type network that we use for matrix inversion. In this framework the adjustable...
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We identify an important class of parallel computations, called ±2b - descend, with an efficient implementation on a hypercube. Given the input A[0: N - 1], a computation in this class consists of log N iteration...
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We present a technique to efficiently simulate a synchronous n-processor PRAM using a completely asynchronous PRAM. this work is an extension of prior results of Martel et. al.[10] in which a measure of work for async...
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An O(N2) heuristic algorithm is presented that embeds all binary trees, with dilation 2 and small average dilation, into the optimal sized hypercube. the heuristic relies on a conjecture about all binary trees with a ...
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Hardware and software considerations regarding communication problems for parallel machines, whose distributed control can be modeled by means of an oriented multigraph without cycles, are presented. the results are a...
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ISBN:
(纸本)0818621419
Hardware and software considerations regarding communication problems for parallel machines, whose distributed control can be modeled by means of an oriented multigraph without cycles, are presented. the results are applied to a pyramidal multi-SIMD (single-instruction multiple-data) architecture, which is very efficient for many low- and intermediate-level image processing and analysis algorithms. A programming style, named coprogramming, is well suited for the design of parallel software for this class of parallel machines.
VLSI hardware architectures of Kanerva's Sparse distributed Memory are described. these architectures are designed for high-speed parallelprocessing with modular expandability. Architectures for an analog address...
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VLSI hardware architectures of Kanerva's Sparse distributed Memory are described. these architectures are designed for high-speed parallelprocessing with modular expandability. Architectures for an analog address comparator and a systolic array have been developed with advanced structures. parallel shift register architecture and parallel comparator architecture with binary tree adders have been studied from an effective VLSI implementation point of view. the realization and performance estimations for each architecture are also presented.
Stochastic rendezvous networks (SRVN) are performance models for multitasking parallel software with intertask communication via rendezvous (RV). the paper describes an approximation for the arrival instant probabilit...
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