there are several ways in which waiting ready tasks can be organized. the two basic organizations are the centralized organization and the distributed organization. the paper considers the impact of task scheduling st...
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A novel architecture of neural networks withdistributed structures which is designed so that each class in the application has a one-output backpropagation subnetwork is presented. A novel architecture (One-Net-One-C...
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A novel architecture of neural networks withdistributed structures which is designed so that each class in the application has a one-output backpropagation subnetwork is presented. A novel architecture (One-Net-One-Class) can overcome the drawbacks of conventional backpropagation architectures which must be completely retrained whenever a class is added. this architecture features complete paralleldistributedprocessing in that the network is comprised of subnetworks each of which is a single output two-layer backpropagation which can be trained and retrieved parallely and independently. the proposed architecture also enjoys rapid convergence in boththe training phase and the retrieving phase.
this paper examines techniques to achieve high speed routing in a distributed memory parallel computer environment. this paper develops a model to analyze the intra-node routing latency, and demonstrates that it may b...
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this paper presents two new parallel algorithms QSPl and QSP2 based on sequential quicksort for sorting data on a mesh multicomputer, and analyzes their scalability using the isoefficiency metric. We show that QSP2 ma...
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A configurable hardware implementation of Kanerva's Sparse distributed Memory has been developed using advanced structures. the system consists of the host computer, address unit and memory unit. the address and m...
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A configurable hardware implementation of Kanerva's Sparse distributed Memory has been developed using advanced structures. the system consists of the host computer, address unit and memory unit. the address and memory units have been implemented with commercially available components to two functioning boards, and they perform the Hamming distance comparison and memory storage functions. In order to achieve effective hardware realization the units are designed for highly parallelprocessing. the host computer is used to edit, compile, and down-load the programs to be run in the units. the performance estimations are also presented.
A novel algorithm for parallel design verification is described. Its data model is that of the data flow computer and is based on the partitioning of the design verification cycle into independent tasks that can be ru...
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ISBN:
(纸本)081862065X
A novel algorithm for parallel design verification is described. Its data model is that of the data flow computer and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. the significance of this methodology is that, unlike other concepts that cannot use the existing sequential code and can only run on an expensive special-purpose hardware, the proposed approach does not require any code development and can be accommodated by a standard UNIX distributed network or a multiprocessor. the author presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network.
Sorting is a classic problem [5], which naturally lends itself to parallelprocessing. Many researchers have investigated memory-based parallel sorting [3], but only a few researchers have investigated the problem of ...
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A coterie under a ground set U consists of a set of subsets (quorums) of U such that any pair of quorums intersect each other. 'Nondominated' coteries are of particular interest, since they are 'optimal...
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Sublinear parallel graph matching algorithms are investigated. the author proposes an approximation scheme for the cardinality matching problem on general graphs that runs in O(k/sup 5/log/sup 4/n) parallel time using...
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Sublinear parallel graph matching algorithms are investigated. the author proposes an approximation scheme for the cardinality matching problem on general graphs that runs in O(k/sup 5/log/sup 4/n) parallel time using O(2/sup k/n/sup 2k+2/) processors on a CREW PRAM parallel machine model. the approximation is at least as big as /sup k///sub k+1/. mod M mod . If the allowed error is a constant, then the algorithm runs in polylogarithmic time using a polynomial number of processors.< >
Presents a randomized algorithm for the multipacket (i.e. k-k) routing problem on an n*n mesh. the algorithm completes with high probability in at the most kn+O(k log n) parallel communication steps, with a constant q...
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Presents a randomized algorithm for the multipacket (i.e. k-k) routing problem on an n*n mesh. the algorithm completes with high probability in at the most kn+O(k log n) parallel communication steps, with a constant queue size of O(k). the previous best known algorithm takes 5/4 kn+O(kn/f(n)) steps with a queue size of O(k f(n)) (for any 1 >
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