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parallel Heuristics for Scalable Community Detection 28

Parallel Heuristics for Scalable Community Detection

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28th ieee International parallel & distributed processing symposium Workshops (IPDPSW)

作者： Lu, Hao Kalyanaraman, Ananth Halappanavar, Mahantesh Choudhury, Sutanay Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99164 USA Pacific Northwest Natl Lab Computat Sci & Math Div Richland WA 99352 USA

ISBN: (纸本)9781479941162

Community detection has become a fundamental operation in numerous graph-theoretic applications. It is used to reveal natural divisions that exist within real world networks without imposing prior size or cardinality constraints on the set of communities. Despite its potential for application, there is only limited support for community detection on large-scale parallel computers, largely owing to the irregular and inherently sequential nature of the underlying heuristics. In this paper, we present parallelization heuristics for fast community detection using the Louvain method as the serial template. the Louvain method is an iterative heuristic for modularity optimization. Originally developed by Blondel et al. in 2008, the method has become increasingly popular owing to its ability to detect high modularity community partitions in a fast and memory-efficient manner. However, the method is also inherently sequential, thereby limiting its scalability. Here, we observe certain key properties of this method that present challenges for its parallelization, and consequently propose heuristics that are designed to break the sequential barrier. For evaluation purposes, we implemented our heuristics using OpenMP multithreading, and tested them over real world graphs derived from multiple application domains (e.g., internet, citation, biological). Compared to the serial Louvain implementation, our parallel implementation is able to produce community outputs with a higher modularity for most of the inputs tested, in comparable number of iterations, while providing real speedups of up to 8x using 32 threads. In addition, our parallel implementation was able to exhibit weak scaling properties on up to 32 threads.

关键词： Community detection Graph coloring Louvain method parallel graph algorithms parallel heuristics

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WECPAR: List Ranking Algorithm and Relative Computational Power 28

WECPAR: List Ranking Algorithm and Relative Computational Po...

引用

28th ieee International parallel & distributed processing symposium Workshops (IPDPSW)

作者： El-Boghdadi, Hatem M. Cairo Univ Fac Engn Dept Comp Engn Giza Egypt

ISBN: (纸本)9781479941162

Reconfigurable models were shown to be very powerful in solving many problems faster than non reconfigurable models. WECPAR W(M,N,k) is an M x N reconfigurable model that has point-to-point reconfigurable interconnection with k wires between neighboring processors. this paper studies several aspects of WECPAR. We first solve the list ranking problem on WECPAR. Some of the results obtained show that ranking one element in a list of N elements can be solved on W(N,N,N) WECPAR in O(1) time. Also, on W(N,N,k), ranking a list L(N) of N elements can be done in O((log N)( inverted right perpendicular log(k) (+1) N inverted left perpendicular )) time. To transfer a large body of algorithms to work on WECPAR and to assess its relative computational power, several simulations algorithms are introduced between WECPAR and well-known models such as PRAM and RMBM. Simulations algorithms show that a PRIORITY CRCW PRAM of N processors and S shared memory locations can be simulated by an W(S, N, k) WECPAR in O( inverted right perpendicular log(k) (+1) N inverted left perpendicular + inverted right perpendicular log S-k (+1) inverted left perpendicular ) time. Also, we show that a PRIORITY CRCW Basic-RMBM(P, B), of P processors and B buses can be simulated by an W(B, P+ B, k) WECPAR in O( inverted right perpendicular log(k) (+1) (P + B) inverted left perpendicular ) time. this has the effect of migrating a large number of algorithms to work directly on WECPAR with the simulation overhead.

关键词： parallel algorithms simulation algorithms list ranking

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A Framework for Lattice QCD Calculations on GPUs

A Framework for Lattice QCD Calculations on GPUs

引用

ieee 28th International parallel & distributed processing symposium (IPDPS)

作者： Winter, F. T. Clark, M. A. Edwards, R. G. Joo, B. Thomas Jefferson Natl Accelerator Facil Newport News VA 23606 USA NVIDIA Corp Santa Clara CA 95050 USA

ISBN: (纸本)9780769552071

Computing platforms equipped with accelerators like GPUs have proven to provide great computational power. However, exploiting such platforms for existing scientific applications is not a trivial task. Current GPU programming frameworks such as CUDA C/C++ require low-level programming from the developer in order to achieve high performance code. As a result porting of applications to GPUs is typically limited to time-dominant algorithms and routines, leaving the remainder not accelerated which can open a serious Amdahl's law issue. the Lattice QCD application Chroma allows us to explore a different porting strategy. the layered structure of the software architecture logically separates the data-parallel from the application layer. the QCD Data-parallel software layer provides data types and expressions with stencil-like operations suitable for lattice field theory. Chroma implements algorithms in terms of this high-level interface. thus by porting the low-level layer one effectively ports the whole application layer in one swing. the QDP-JIT/PTX library, our reimplementation of the low-level layer, provides a framework for Lattice QCD calculations for the CUDA architecture. the complete software interface is supported and thus applications can be run unaltered on GPU-based parallel computers. this reimplementation was possible due to the availability of a JIT compiler which translates an assembly language (PTX) to GPU code. the existing expression templates enabled us to employ compile-time computations in order to build code generators and to automate the memory management for CUDA. Our implementation has allowed us to deploy the full Chroma gauge-generation program on large scale GPU-based machines such as Titan and Blue Waters and accelerate the calculation by more than an order of magnitude.

关键词： Application framework C++ CUDA GPU JIT Lattice QCD PTX Lattice QCD GRAPPER PICK UP Graphics processing Unit Application Framework just in time compiler data parallel application layer Store management LOW LEVEL Code generation Chroma Frameworks software interface

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Online Error Detection and Recovery in Dataflow Execution

Online Error Detection and Recovery in Dataflow Execution

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ieee 20th International On-Line Testing symposium (IOLTS)

作者： Alves, Tiago A. O. Kundu, Sandip Marzulo, Leandro A. J. Franca, Felipe M. G. Univ Fed Rio de Janeiro Programa Engn Sistemas & Comp COPPE Rio de Janeiro Brazil Univ Estado Rio De Janeiro Inst Matemat Estatist Rio De Janeiro Brazil Univ Massachusetts Dept Elect & Comp Engn Amherst MA USA

ISBN: (纸本)9781479953240

the processor industry is well on its way towards manycore processors that comprise of large number of simple cores. the shift towards multi and manycores calls for new programming paradigms suitable for exploiting the inherent parallelism in applications. Dataflow execution was shown to be a good option for programming in such enviromnents. It is well-known that as CMOS technology continues to scale, it becomes more prone to transient and permanent hardware faults. In this paper we present a novel mechanism for error detection and recovery that focuses on transient errors in dataflow execution. Due to the inherently parallel nature of dataflow, our solution is completely distributed and synchronizes only cores that have data dependencies between them, as opposed to prior work on error recovery that in general rely on global synchronization of the system. We evaluate the proposed solution via a software implementation on top of a dataflow runtime. Experimental results show that error detection overhead is highly related to the pressure on the memory bus. In memory bound applications, performance is found to deteriorate, while for other benchmarks, the observed overhead is less than 23%. We find no comparable previous work to contrast these results.

关键词： Benchmark testing Bit error rate Hardware Image edge detection parallel processing Runtime Transient analysis Benchmark testing Edge detection Runtime data flow Transient analysis parallel processing (COMPUTERS) Bit error rate Computer hardware Error detection and recovery software implementation synchronous system transient errors Legal Executions

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AUModel: A conceptual model for adaptive software 5

AUModel: A conceptual model for adaptive software

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2014 5th ieee International Conference on Software Engineering and Service Science, ICSESS 2014

作者： Liu, Hui Ding, Bo Shi, Dianxi Wang, Huaimin National Key Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha Hunan410073 China

ISBN: (纸本)9781479932788

Pervasive software should be able to adapt itself to the changing environments and user requirements. Obviously, it will bring great challenges to the software engineering practice. this paper proposes AUModel, a conceptual model for adaptive software, which takes adaptability as an inherent feature and can act as the foundation of the engineering process. By introducing AUModel, the reuse of software adaptation infrastructure as well as the separation of adaptation concerns are enabled, which can facilitate both the development and maintenance of adaptive software. this paper also presents our initial attempts to realize this model, including a middleware prototype to support this model and an application to validate its effectiveness. © 2014 ieee.

关键词： Middleware

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A study of feedforward control on stability of grid-parallel inverter with various grid impedance

A study of feedforward control on stability of grid-parallel...

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2014 ieee 5th International symposium on Power Electronics for distributed Generation Systems, PEDG 2014

作者： Wang, Jing Song, Yulun Monti, A. Institute for Automation of Complex Power Systems E. on Energy Research Centre Aachen Germany

ISBN: (纸本)9781479951154

the Current Controlled Voltage Source Inverter (CCVSI) has attracted substantial research due to its common application for the integration of renewable energy resources into the main grid. the single loop current controller is commonly used in industry for CCVSI due to its simplicity, desirable stability margins and dynamic performance. For the single loop controller, the point of common coupling (PCC) voltage feedforward control is used to improve the transient and disturbance rejection performance. However, this solution exhibits one drawback that has not yet been adequately discussed in the literature: the poor stability caused by the feedforward control itself. It is proved that the feedforward voltage results in a 'positive feedback control' which essentially degrades the stability of the system and its control performance. Since the gain of the 'positive feedback control' depends on the grid impedance, it is necessary to study how the stability and control performance of the grid parallel inverter is affected by the feedforward control under various grid impedances. the system without feedforward control is also investigated due the fact that the grid impedance generally affects the system stability. the analytical study shows that two cases have similar performance under stiff grid, while the case without feedforward has superior stability and control performance under weak grid impedance. the simulation and experimental results also validate the outcome of the analytical study. © 2014 ieee.

关键词： Feedback control

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Training Large Scale Deep Neural Networks on the Intel Xeon Phi Many-core Coprocessor 28

Training Large Scale Deep Neural Networks on the Intel Xeon ...

引用

28th ieee International parallel & distributed processing symposium Workshops (IPDPSW)

作者： Jin, Lei Wang, Zhaokang Gu, Rong Yuan, Chunfeng Huang, Yihua Nanjing Univ Dept Comp Sci & Technol Natl Key Lab Novel Software Technol Nanjing 210023 Jiangsu Peoples R China

ISBN: (纸本)9781479941162

As a new area of machine learning research, the deep learning algorithm has attracted a lot of attention from the research community. It may bring human beings to a higher cognitive level of data. Its unsupervised pre-training step allows us to find high-dimensional representations or abstract features which work much better than the principal component analysis (PCA) method. However, it will face problems when being applied to deal with large scale data due to its intensive computation from many levels of training process against large scale data. the sequential deep learning algorithms usually can not finish the computation in an acceptable time. In this paper, we propose a many-core algorithm which is based on a parallel method and is used in the Intel Xeon Phi many-core systems to speed up the unsupervised training process of Sparse Autoencoder and Restricted Boltzmann Machine (RBM). Using the sequential training algorithm as a baseline to compare, we adopted several optimization methods to parallelize the algorithm. the experimental results show that our fully-optimized algorithm gains more than 300-fold speedup on parallelized Sparse Autoencoder compared with the original sequential algorithm on the Intel Xeon Phi coprocessor. Also, we ran the fully-optimized code on both the Intel Xeon Phi coprocessor and an expensive Intel Xeon CPU. Our method on the Intel Xeon Phi coprocessor is 7 to 10 times faster than the Intel Xeon CPU for this application. In addition to this, we compared our fully-optimized code on the Intel Xeon Phi with a Matlab code running on single Intel Xeon CPU. Our method on the Intel Xeon Phi runs 16 times faster than the Matlab implementation. the result also suggests that the Intel Xeon Phi can offer an efficient but more general-purposed way to parallelize the deep learning algorithm compared to GPU. It also achieves faster speed with better parallelism than the Intel Xeon CPU.

关键词： Deep learning Unsupervised learning Deep architecture Sparse autoencoder Restricted Boltzmann Machine parallel algorithm Intel Xeon Phi Many-core

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Automating distributed partial aggregation 5

Automating distributed partial aggregation

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5th ACM symposium on Cloud Computing, SOCC 2014

作者： Liu, Chang Zhang, Jiaxing Zhou, Hucheng McDirmid, Sean Guo, Zhenyu Moscibroda, thomas University of Maryland College Park United States Microsoft Research United States

ISBN: (纸本)1595930361

Partial aggregation is of great importance in many distributed data-parallel systems. Most notably, it is commonly applied by MapReduce programs to optimize I/O by successively aggregating partially reduced results into a final result, as opposed to aggregating all input records at once. In spite of its importance, programmers currently enable partial aggregation by tediously encoding their reduce functionality into separate reduce and combine functions. this is error prone and often leads to missed optimization opportunities. this paper proposes an algorithm that automatically verifies if the original monolithic reduce function of a MapReduce program is eligible for partial aggregation, and if so, synthesizes enabling partial aggregation code. the key insight behind this algorithm is a novel necessary and sufficient condition for when partial aggregation is applicable to a reduce function. this insight provides us with a formal foundation for an automaton, which derives a satisfiability problem that can be fed into a standard SMT solver. By doing so, we transform the problem of synthesis into a program inversion problem, which is however nondeterministic. Although such inversion is hard to solve in general, we observe that most reducers in practical distributed computing contexts can be classified into a few categories for which we can design efficient synthesis algorithms. Finally, we build and evaluate a prototype of our method to demonstrate its feasibility in the SCOPE distributed data-parallel system. Copyright © 2014 by the Association for ComputingMachinery, Inc.

关键词： MapReduce

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Delayed switch: Cloud service upgrade with low availability and capacity loss 5

Delayed switch: Cloud service upgrade with low availability ...

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2014 5th ieee International Conference on Software Engineering and Service Science, ICSESS 2014

作者： Ouyang, Xue Ding, Bo Wang, Huaimin Parallel and Distributed Laboratory School of Computer Science National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781479932788

Cloud services must upgrade continuously in order to maintain competitive. However, a large body of empirical evidence suggests that, upgrade procedures used in practice are failure-prone and often cause planned or unplanned downtime. In this paper, we first define what is cloud service online upgrade, and then we analyze the shortcomings of current mainstream cloud service online upgrade mechanisms. In particular, the mixed version problem along with rolling upgrade and the capacity loss problem brought by split mode upgrade have been discussed. After that, we propose a solution called Delayed Switch, which can conduct cloud service upgrade with lower loss of availability and capacity in contrast with existing approaches. We prove the performance of delayed switch in theory and develop a prototype system applying this method. And by conducting experiments with a typical e-commerce service named Rubis, we validate the effectiveness and efficiency of our approach. © 2014 ieee.

关键词： distributed database systems

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proceedings - International symposium on parallel Architectures, Algorithms and Programming, PAAP

Proceedings - International Symposium on Parallel Architectu...

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6th International symposium on parallel Architectures, Algorithms, and Programming, PAAP 2014

ISBN: (纸本)9781479938445

the proceedings contain 56 papers. the topics discussed include: design and evaluation of dynamically-allocated multi-queue buffers with multiple packets for NoC routers;algorithmic aspects for bi-objective multiple-choice hardware/software partitioning;fault-tolerant distributed publish/subscribe using self-stabilization;a runtime framework for GPGPU;a sensitive and robust grid reputation system based on rating of recommenders;efficient FPGA-mapping of 1024 point FFT pipeline SDF processor;multi-parameter online identification algorithm of induction motor for hybrid electric vehicle applications;wide area power system fault detection using compressed sensing to reduce the WAN data traffic;PSO applied to optimal operation of a micro-grid with wind power;and a fuzzy multi-objective optimization method solving the output of energy storage system.

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