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GPU Accelerated Elliptic Curve Cryptography in GF(2^m)

GPU Accelerated Elliptic Curve Cryptography in <i>GF</i>(2<i...

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53rd Midwest symposium on Circuits and Systems (MWSCAS 2010)

作者： Cohen, Aaron E. Parhi, Keshab K. Univ Technol Ctr Leanics Corp 1313 5th St SE Minneapolis MN 55414 USA Univ Minnesota Minneapolis Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)9781424477739

this paper presents the Graphics processing Unit (GPU) accelerated version of the LSB Invariant scalar point multiplication for binary elliptic curves. this method was implemented using the CUDA programming language for nVidia graphics cards. With a parallel factor of (length+1) and Lopez-Dahab projective coordinate P-i's, on an nVidia GTX 285 graphics card precomputation takes 190.203995 ms while the actual scalar point multiplication takes 173.121002 ms for GF(2(163)). With a parallel factor of (length+1)*(length) and Lopez-Dahab projective coordinate P-i's, on an nVidia GTX 285 graphics card precomputation of 2(i)P points takes 9.545 ms while the actual scalar point multiplication takes 10.743 ms (similar to 93.0839 kP/s) for GF(2(163)). With a parallel factor of (length+1)*(length) and affine coordinate P-i's, on an nVidia GTX 285 graphics card precomputation takes 140.078003 ms for GF(2(163)) while the actual scalar point multiplication takes 10.363000 ms (similar to 96.4972 kP/s) for GF(2(163)).

关键词： GPU Cryptography Elliptic Curves Multicore

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Image Edge Detection Based on FPGA

Image Edge Detection Based on FPGA

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9th International symposium on distributed Computing and Applications to Business, Engineering and Science (DCABES 2010)

作者： Guo, Zhengyang Xu, Wenbo Chai, Zhilei Jiangnan Univ Sch Informat Technol Wuxi Peoples R China

ISBN: (纸本)9780769541105

Field Programmable Gate Array (FPGA) is an effective device to realize real-time parallel processing of vast amounts of video data because of the fine-grain reconfigurable structures. this paper presents a kind of parallel processing construction of Sobel edge detection enhancement algorithm, which can quickly get the result of one pixel in only one clock periods. the algorithm is designed with a FPGA chip called XC3S200- 5ft256, and it can process 1024x1024x8 Gray Scale Image successfully. the design can locate the edge of the gray image quickly and efficiently.

关键词： Edge detection Sobel operator FPGA Real-time parallel processing

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A hybrid interest management mechanism for peer-to-peer networked virtual environments

A hybrid interest management mechanism for peer-to-peer netw...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Pan, Kec Cai, Wentong Tang, Xueyan Zhou, Suiping Turner, Stephen John Parallel and Distributed Computing Center School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore

ISBN: (纸本)9781424464432

An Interest Management (IM) mechanism eliminates irrelevant status updates transmitted in Networked Virtual Environments (NVE). However, IM itself involves both computation and communication overhead, of which the latter is the focus of this paper. Traditionally, there are area-based and cell-based IM mechanisms. this paper proposes a hybrid IM mechanism for peer-to-peer NVEs, that utilizes the cell-based mechanism to reduce Area-Of-Interest (AOI) updates in the area-based mechanism so as to reduce its communication overhead. To compare the new mechanism with the two traditional approaches, a multiplayer game scenario is simulated. the performance results show that, compared to the traditional mechanisms, the hybrid mechanism reduces the upload bandwidth consumption by more than 25.28 percent, reduces the overhead ratio from more than 67.54 percent to only 25.17 percent, and allows more than 5000 players in the Internet to join the same game with today's network upload bandwidth. © 2010 ieee.

关键词： Environmental management

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proceedings - 2010 ieee International Conference on Networking, Architecture and Storage, NAS 2010

Proceedings - 2010 IEEE International Conference on Networki...

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5th ieee International Conference on Networking, Architecture and Storage, NAS 2010

ISBN: (纸本)9780769541341

the proceedings contain 57 papers. the topics discussed include: label-based DV-Hop localization against wormhole attacks in wireless sensor networks;a simple group key management approach for mobile ad hoc networks;a fine-grained data reconstruction algorithm for solid-state disks;a distributed approach for hidden wormhole detection with neighborhood information;a high effective indexing and retrieval method providing block-level timely recovery to any point-in-time;characterizing the dependability of distributed storage systems using a two-layer hidden Markov model-based approach;fault tolerant data collection in heterogeneous intelligent monitoring networks;a probabilistic routing protocol for heterogeneous sensor networks;time-bounded essential localization for wireless sensor networks;stabilizing path modification of power-aware on/off interconnection networks;and fast and memory-efficient traffic classification with deep packet inspection in CMP architecture.

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Tile QR factorization with parallel panel processing for multicore architectures

Tile QR factorization with parallel panel processing for mul...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Hadri, Bilel Ltaief, Hatem Agullo, Emmanuel Dongarra, Jack Department of Electrical Engineering and Computer Science University of Tennessee Knoxville TN United States Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge TN United States School of Mathematics School of Computer Science University of Manchester United Kingdom

ISBN: (纸本)9781424464432

To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of tasks of fine granularity where nodes represent tasks, either panel factorization or update of a block-column, and edges represent dependencies among them. Although past approaches already achieve high performance on moderate and large square matrices, their way of processing a panel in sequence leads to limited performance when factorizing tall and skinny matrices or small square matrices. We present a new fully asynchronous method for computing a QR factorization on shared-memory multicore architectures that overcomes this bottleneck. Our contribution is to adapt an existing algorithm that performs a panel factorization in parallel (named Communication-Avoiding QR and initially designed for distributed-memory machines), to the context of tile algorithms using asynchronous computations. An experimental study shows significant improvement (up to almost 10 times faster) compared to state-of-the-art approaches. We aim to eventually incorporate this work into the parallel Linear Algebra for Scalable Multi-core Architectures (PLASMA) library. © 2010 ieee.

关键词： Directed graphs

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parallel I/O performance: From events to ensembles

Parallel I/O performance: From events to ensembles

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Uselton, Andrew Howison, Mark Wright, Nicholas J. Skinner, David Keen, Noel Shalf, John Karavanic, Karen L. Oliker, Leonid CRD/NERSC Lawrence Berkeley National Laboratory Berkeley CA 94720 United States Portland State University Portland OR 97207-0751 United States

ISBN: (纸本)9781424464432

parallel I/O is fast becoming a bottleneck to the research agendas of many users of extreme scale parallel computers. the principle cause of this is the concurrency explosion of high-end computation, coupled with the complexity of providing parallel file systems that perform reliably at such scales. More than just being a bottleneck, parallel I/O performance at scale is notoriously variable, being influenced by numerous factors inside and outside the application, thus making it extremely difficult to isolate cause and effect for performance events. In this paper, we propose a statistical approach to understanding I/O performance that moves from the analysis of performance events to the exploration of performance ensembles. Using this methodology, we examine two I/O-intensive scientific computations from cosmology and climate science, and demonstrate that our approach can identify application and middleware performance deficiencies - resulting in more than 4× run time improvement for both examined applications. © 2010 ieee.

关键词： File organization

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A scheduling framework for large-scale, parallel, and topology-aware applications

A scheduling framework for large-scale, parallel, and topolo...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Kravtsov, Valentin Bar, Pavel Carmeli, David Schuster, Assaf Swain, Martin Computer Science Department Technion - Israel Institute of Technology Technion City Haifa Israel Systems Biology Research Group University of Ulster Cromore Road Coleraine BT52 1SA Northern Ireland United Kingdom

ISBN: (纸本)9781424464432

Scheduling of large-scale, distributed topology-aware applications requires that not only the properties of the requested machines be considered, but also the properties of the machines' interconnections. this requirement severely complicates the scheduling process, as even a matching between a single multi-processors task and available machines in a single time slot becomes an NP-complete problem with no polynomial approximation. In this paper we propose a complete scheduling framework for multi-cluster, heterogeneous environments that provides, in practice, an efficient solution for the scheduling of topology-aware applications. the proposed framework is very flexible as it is composed of pluggable components and can be easily configured to support a variety of scheduling policies. We also describe three novel scheduling and coallocation algorithms that were developed and plugged into the framework. the proposed scheduling framework was integrated into the QosCosGrid1 system, where it is used as the main decision-making module. © 2010 ieee.

关键词： Scheduling

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On-line detection of large-scale parallel application's structure

On-line detection of large-scale parallel application's stru...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Llort, German Gonzalez, Juan Servat, Harald Gimenez, Judit Labarta, Jesus Barcelona Supercomputing Center Universitat Politècnica de Catalunya Barcelona Spain

ISBN: (纸本)9781424464432

With larger and larger systems being constantly deployed, trace-based performance analysis of parallel applications has become a challenging task. Even if the amount of performance data gathered per single process is small, traces rapidly become unmanageable when merging together the information collected from all processes. In general, an efficient analysis of such a large volume of data is subject to a previous filtering step that directs the analyst's attention towards what is meaningful to understand the observed application behavior. Furthermore, the iterative nature of most scientific applications usually ends up producing repetitive information. Discarding irrelevant data aims at reducing both the size of traces, and the time required to perform the analysis and deliver results. In this paper, we present an on-line analysis framework that relies on clustering techniques to intelligently select the most relevant information to understand how the application behaves, while keeping the volume of performance data at a reasonable size. © 2010 ieee.

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Efficient exhaustive verification of the collatz conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs

Efficient exhaustive verification of the collatz conjecture ...

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2010 ieee International symposium on parallel and distributed processing, Workshops and Phd Forum, IPDPSW 2010

作者： Ito, Yasuaki Nakano, Koji Department of Information Engineering Hiroshima University Kagamiyama 1-4-1 Higashi-Hiroshima 739-8527 Japan

ISBN: (纸本)9781424465347

Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. the Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. the main contribution of this paper is to present an efficient implementation of a coprocessor that performs the exhaustive search to verify the Collatz conjecture using a DSP48E Xilinx Virtex-5 blocks, each of which contains one multiplier and one adder. the experimental results show that, our coprocessor can verify 3.88 × 108 64-bit numbers per second. © 2010 ieee.

关键词： Coprocessor

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Large neighborhood local search optimization on graphics processing units

Large neighborhood local search optimization on graphics pro...

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2010 ieee International symposium on parallel and distributed processing, Workshops and Phd Forum, IPDPSW 2010

作者： Van Luong, thé Melab, Nouredine Talbi, El-Ghazali INRIA Lille Nord Europe CNRS LIFL Parc Scientifique de la Haute Borne 40 avenue Halley Bat. A Park Plaza 59650 Villeneuve d'Ascq France

ISBN: (纸本)9781424465347

Local search (LS) algorithms are among the most powerful techniques for solving computationally hard problems in combinatorial optimization. these algorithms could be viewed as "walks through neighborhoods" where the walks are performed by iterative procedures that allow to move from a solution to another one in the solution space. In these heuristics, designing operators to explore large promising regions of the search space may improve the quality of the obtained solutions at the expense of a highly computationally process. therefore, the use of graphics processing units (GPUs) provides an efficient complementary way to speed up the search. However, designing applications on GPU is still complex and many issues have to be faced. We provide a methodology to design and implement large neighborhood LS algorithms on GPU. the work has been experimented for binary problems by deploying multiple neighborhood structures. the obtained results are convincing both in terms of efficiency, quality and robustness of the provided solutions at run time.© 2010 ieee.

关键词： Graphics processing unit

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