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proceedings - 14th ieee/ACM International symposium on distributed Simulation and Real-Time Applications, DS-RT 2010

Proceedings - 14th IEEE/ACM International Symposium on Distr...

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14th ieee/ACM International symposium on distributed Simulation and Real-Time Applications, DS-RT 2010

ISBN: (纸本)9780769542515

the proceedings contain 29 papers. the topics discussed include: getting from here to there: locomotion in virtual environments;self-adaptive dynamic load balancing for large-scale HLA-based simulations;supporting the decentralized development of large-scale distributed real-time LVC simulation systems with TENA (the test and training enabling architecture);scale virtual worlds through dynamic load balancing;synchronization of images from multiple cameras to reconstruct a moving human;synchronized range queries in distributed simulations of multi-agent systems;kiltera: a language for timed, event-driven, mobile and distributed simulation;battle management language enables rapid integration of command & control with simulation;scenario based modeling for very large scale simulations;understanding and building interoperable, integrable and composable distributed training simulations;and global lookahead management (GLM) protocol for conservative DEVS simulation.

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Balls into non-uniform bins

Balls into non-uniform bins

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Berenbrink, Petra Brinkmann, André Friedetzky, Tom Nagel, Lars School of Computing Science Simon Fraser University Burnaby BC V5A 1S6 Canada Paderborn Center for Parallel Computing University of Paderborn 33102 Paderborn Germany School of Engineering and Computing Sciences Durham University Durham DH1 3LE United Kingdom

ISBN: (纸本)9781424464432

Balls-into-bins games for uniform bins are widely used to model randomized load balancing strategies. Recently, balls-into-bins games have been analysed under the assumption that the selection probabilities for bins are not uniformly distributed. these new models are motivated by properties of many peer-to-peer (P2P) networks, which are not able to perfectly balance the load over the bins. While previous evaluations try to find strategies for uniform bins under nonuniform bin selection probabilities, this paper investigates heterogeneous bins, where the "capacities" of the bins might differ significantly. We show that heterogeneous environments can even help to distribute the load more evenly, and that the load difference between bins can be bounded by O(log log n) if each ball has two random choices, where n is the number of bins. Our analysis and simulation results show, for the first time, that the maximum load in heterogeneous balls-into-bins games is independent from the overall system capacity C and that bigger bins therefore can help to achieve good load balancing properties. © 2010 ieee.

关键词： Peer to peer networks

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Efficient parallel algorithms for maximum-density segment problem

Efficient parallel algorithms for maximum-density segment pr...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Wang, Xue Qiu, Fasheng Prasad, Sushil K. Chen, Guantao Computer Science Georgia State University Atlanta United States Mathematics and Statistics Georgia State University Atlanta United States

ISBN: (纸本)9781424464432

One of the fundamental problems involving DNA sequences is to find high density segments of certain widths, for example, those regions with intensive guanine and cytosine (GC). Formally, given a sequence, each element of which has a value and a width, the maximum-density segment problem asks for the segment with the maximum density while satisfying minimum and possibly maximum width constraints. While several linear-time sequential algorithms have emerged recently due to its primitive-like utility, to our knowledge, no nontrivial parallel algorithm has yet been proposed for this topical problem. In this paper, we propose an 0(log2 n)-time CREW PRAM algorithm using n processors to solve the generalized maximum-density problem, with a minimum width constraint and non-uniform widths. Besides, we describe an efficient implementation of the parallel algorithm on manycore GPUs (nVIDIA GeForce GTX 280), taking advantage of the full programmability of CUDA. this algorithm can process up to million-size sequence within a second using an nVIDIA GeForce GTX 280, thus demonstrating the practicality of this algorithm as a basic primitive for scientists. this may also indicate suitability of modern GPU architectures as implementation platform for certain PRAM algorithms. © 2010 ieee.

关键词： Graphics processing unit

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A parallel architecture for meaning comparison

A parallel architecture for meaning comparison

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Mohan, Suneil Biswas, Amitava Tripathy, Aalap Pannigrahy, Jagannath Mahapatra, Rabi Department of Computer Science and Engineering Texas A and M University College Station TX United States

ISBN: (纸本)9781424464432

In this paper we present a fine grained parallel architecture that performs meaning comparison using vector cosine similarity (dot product). Meaning comparison assigns a similarity value to two objects (e.g. text documents) based on how similar their meanings (represented as two vectors) are to each other. the novelty of our design is the fine grained parallelism which is not exploited in available hardware based dot product processor designs and can not be achieved in traditional server class processors like the Intel Xeon. We compare the performance of our design against that of available hardware based dot product processors as well a server class processor using optimum software code performing the same computation. We show that our hardware design can achieve a speedup of 62,000 times compared to an available hardware design and a speedup of 8866 times with 33% (1.5 times) less power consumption, compared to software code running on Intel Xeon processor for 1024 basis vectors. Our design can significantly reduce the amount of servers required for similarity comparison in a distributed search engine. thus it can enable reduction in energy consumption, investment, operational costs and floor area in search engine data centers. this design can also be deployed for other applications which require fast dot product computation. © 2010 ieee.

关键词： Green computing

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Towards execution guarantees for stream queries

Towards execution guarantees for stream queries

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2010 ieee International symposium on parallel and distributed processing, Workshops and Phd Forum, IPDPSW 2010

作者： Fernández-Moctezuma, Rafael J. Maier, David Tufte, Kristin A. Department of Computer Science Portland State University 1900 SW 4th Ave. Portland OR 97207 United States

ISBN: (纸本)9781424465347

the unbounded nature of data streams and the lowlatency requirements of stream processing present interesting challenges in Data Stream Management System (DSMS) design. Streaming query operators are typically designed to produce results with low latency, as well as to efficiently manage their state. Stream-progress delimitation techniques, such as punctuation, can help query operators achieve these goals. In this work, we look at deriving execution guarantees with respect to result production and state management for complete queries over punctuated streams. these guarantees are derived before query execution. We formalize notions of successful stream processing at an operator level, and extend these definitions to stream queries as a whole. We introduce a framework, punctuation contracts, for analyzing data processing and punctuation propagation from input to output on individual operators. We then use our framework to analyze complete queries and determine, prior to execution, if every valid input is eventually emitted, and no item remains in operator state indefinitely. Finally, we discuss extensions needed to bound query memory requirements;we describe four stream properties that can be used to help understand and quantify memory and CPU usage. © 2010 ieee.

关键词： Information management

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Improvement of Voltage Unbalance and Voltage Sag in Radial Distribution Systems Using DG

Improvement of Voltage Unbalance and Voltage Sag in Radial D...

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5th ieee Conference on Industrial Electronics and Applications

作者： Saidian, Ali Heidari, Mehrdad Mirabbasi, Davar Shahid Chamran Univ Ahvaz Iran

ISBN: (纸本)9781424450466

Most of the dispersed generation systems (DGS) have smaller installation capacity and have to be connected to the distribution network to supply electric power into the utility as well as local loads. When the DG is interconnected in parallel with the utility distribution system, some operating conflicts might arise that affect the system power quality. this paper investigate the effect of DG on the distribution network, with more focusing on power quality issues especially voltage quality issues like voltage sag and voltage unbalance. To confirm this subject, simulation results are provided to reveal the effect of DG on power quality. the purpose of the simulation is to study the effect of different sizes of synchronous DG on voltage regulation, voltage sag and voltage unbalance in two cases: without local load and with RL local load. the simulation is performed using MATLAB/SIMULINK.

关键词： distributed Generation (DG) voltage unbalance voltage sag

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An auto-tuning framework for parallel multicore stencil computations

An auto-tuning framework for parallel multicore stencil comp...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Kamil, Shoaib Chan, Cy Oliker, Leonid Shall, John Williams, Samuel CRD/NERSC Lawrence Berkeley National Laboratory Berkeley CA 94720 United States EECS Department University of California at Berkeley Berkeley CA 94720 United States CSAIL Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)9781424464432

Although stencil auto-tuning has shown tremendous potential in effectively utilizing architectural resources, it has hitherto been limited to single kernel instantiations;in addition, the large variety of stencil kernels used in practice makes this computation pattern difficult to assemble into a library. this work presents a stencil auto-tuning framework that significantly advances programmer productivity by automatically converting a straightforward sequential Fortran 95 stencil expression into tuned parallel implementations in Fortran, C, or CUDA, thus allowing performance portability across diverse computer architectures, including the AMD Barcelona, Intel Nehalem, Sun Victoria Falls, and the latest NVIDIA GPUs. Results show that our generalized methodology delivers significant performance gains of up to 22× speedup over the reference serial implementation. Overall we demonstrate that such domain-specific auto-tuners hold enormous promise for architectural efficiency, programmer productivity, performance portability, and algorithmic adaptability on existing and emerging multicore systems. © 2010 ieee.

关键词： Computer architecture

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Fault-tolerance for PastryGrid middleware

Fault-tolerance for PastryGrid middleware

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2010 ieee International symposium on parallel and distributed processing, Workshops and Phd Forum, IPDPSW 2010

作者： Abbes, Heithem Cérin, Christophe Jemni, Mohamed Missaoui, Yazid LIPN CNRS UMR 7030 Université Paris 13 99 avenue Jean-Baptiste Clément 93430 Villetaneuse France Research Unit UTIC ESSTT University of Tunis 5 Av. Taha Hussein Bab Mnara Tunis Tunisia

ISBN: (纸本)9781424465347

this paper analyses the performance of a decentralized and fault-tolerant software layer for Desktop Grid resources management. the grid middle- ware under concern is named PastryGrid. Its main de- sign principle is to eliminate the need for a centralized server, therefore to remove the single point of failure and bottleneck of existing Desktop Grids. PastryGrid (based on Pastry) supports the execution of distributed application with precedence between tasks in a decen- tralized way. Indeed, each node can play alternatively the role of client or server. Our main contribution is to propose a fault tolerant mechanism for PastryGrid middleware. Since the management of PastryGrid is distributed over the participants without central manager, its control becomes a challenging problem, especially when dealing with faults. the experimental results on the Grid'5000 testbed demonstrate that our decentralized fault-tolerant system is robust because it supports high fault rates. © 2010 ieee.

关键词： Middleware

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Blocking LU Decomposition for FPGAs

Blocking LU Decomposition for FPGAs

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18th ieee Annual International symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Wu, Guiming Dou, Yong Peterson, Gregory D. Natl Univ Def Technol Natl Lab Parallel & Distributed Proc Changsha 410073 Hunan Peoples R China Univ Tennessee Elect Engn & Comp Sci Knoxville TN 37996 USA

ISBN: (纸本)9780769540566

To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is applicable for matrices of arbitrary size. We introduce a high performance hardware design, which mainly consists of a linear array of processing elements (PEs), to implement our block LU decomposition algorithm. A total of 36 PEs can be integrated into a Xilinx Virtex-5 xc5vlx330 FPGA on our self-designed PCI-Express card, reaching a sustained performance of 8.50 GFLOPS at 133 MHz, which outperforms previous work.

关键词： LU decomposition linear arrays

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A novel application of parallel betweenness centrality to power grid contingency analysis

A novel application of parallel betweenness centrality to po...

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24th ieee International parallel and distributed processing symposium, IPDPS 2010

作者： Jin, Shuangshuang Huang, Zhenyu Chen, Yousu Chavarría-Miranda, Daniel Feo, John Wong, Pak Chung Pacific Northwest National Laboratory Richland WA 99354 United States

ISBN: (纸本)9781424464432

In Energy Management Systems, contingency analysis is commonly performed for identifying and mitigating potentially harmful power grid component failures. the exponentially increasing combinatorial number of failure modes imposes a significant computational burden for massive contingency analysis. It is critical to select a limited set of high- impact contingency cases within the constraint of computing power and time requirements to make it possible for real-time power system vulnerability assessment. In this paper, we present a novel application of parallel betweenness centrality to power grid contingency selection. We cross-validate the proposed method using the model and data of the western US power grid, and implement it on a Cray XMT system - a massively multithreaded architecture - leveraging its advantages for parallel execution of irregular algorithms, such as graph analysis. We achieve a speedup of 55 times (on 64 processors) compared against the single-processor version of the same code running on the Cray XMT. We also compare an OpenMP-based version of the same code running on an HP Superdome shared-memory machine. the performance of the Cray XMT code shows better scalability and resource utilization, and shorter execution time for large-scale power grids. this proposed approach has been evaluated in PNNL's Electricity Infrastructure Operations Center (EIOC). It is expected to provide a quick and efficient solution to massive contingency selection problems to help power grid operators to identify and mitigate potential widespread cascading power grid failures in real time. © 2010 ieee.

关键词： parallel processing systems

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