the aim of this paper is to identify the requirements on data that are necessary to support a collective intelligence solution for future supply chains. It is based on an evidential discussion of the information flows...
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We propose the use of windowed kriging to enable ordinary kriging to interpolate sampled natural images of much higher resolution. Due to its high computational cost, applying ordinary kriging on a whole image can int...
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We propose the use of windowed kriging to enable ordinary kriging to interpolate sampled natural images of much higher resolution. Due to its high computational cost, applying ordinary kriging on a whole image can interpolate samples from only 5% of a 64×64 image, while windowed kriging can process images with resolutions higher than 512×512 pixels. Our proposal is motivated by our vision of real-time near-natural collaboration from distributed places based on distributed Multimedia Plays (DMP) architecture that is realizable in another decade. Windowed kriging allows parallel transmission and compression of sampled natural images to facilitate controlled packets dropping by network nodes for graceful video quality degradation with guaranteed maximum end-to-end delay. Our simple window scheme makes parallel interpolation at the receiver side possible, for which a design of parallel hardware implementation is presented. Typical artifacts due to applying the technique can easily be eliminated completely to produce images of decent quality.
In wireless sensor networks, sensor nodes are capable of not only measuring real world phenomena, but also storing, processing, and transferring these measurements. Many techniques have been proposed for storing and r...
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To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is app...
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To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is applicable for matrices of arbitrary size. We introduce a high performance hardware design, which mainly consists of a linear array of processing elements (PEs), to implement our block LU decomposition algorithm. A total of 36 PEs can be integrated into a Xilinx Virtex-5 xc5vlx330 FPGA on our self-designed PCI-Express card, reaching a sustained performance of 8.50 GFLOPS at 133 MHz, which outperforms previous work.
In the popular video coding trend, the encoder has the task to exploit both spatial and temporal redundancies present in the video sequence, which is a complex procedure;As a result almost all video encoders have five...
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the proceedings contain 145 papers. the topics discussed include: a Kalman filter based fast noise suppression algorithm;multiband excitation for speech enhancement;distributed audio coding with efficient source corre...
ISBN:
(纸本)9781424436774
the proceedings contain 145 papers. the topics discussed include: a Kalman filter based fast noise suppression algorithm;multiband excitation for speech enhancement;distributed audio coding with efficient source correlation extraction;a temporally varying objective audio quality metric;spectral multi-scale analysis for multi-pitch tracking;a low complexity noise suppressor with hybrid filterbanks and adaptive time-frequency tiling;speaker identification in room reverberation using GMM-UBM;comparison of localization algorithms using attenuation estimates;learning the intrinsic dimensions of the timit speech database with maximum variance unfolding;closed-form MSE performance of the distributed LMS algorithm;a simplified predistorter for distortion compensation of parallel Wiener-type systems based on direct learning architecture;and fundamental issues in the stability of adaptive IIR filters.
Nowadays, common systems in the area of high performance computing exhibit highly hierarchical architectures. As a result, achieving satisfactory;application performance demands an adaptation of the respective paralle...
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ISBN:
(纸本)9781424437511
Nowadays, common systems in the area of high performance computing exhibit highly hierarchical architectures. As a result, achieving satisfactory;application performance demands an adaptation of the respective parallel algorithm to such systems. this, in turn, requires knowledge about the actual hardware structure even at the application level. However, the prevalent Message Passing Interface (MPI) standard (at least in its current version 2.1) intentionally hides heterogeneity from the application programmer in order to assure portability In this paper, we introduce the MPIXternal library which tries to Circumvent this obvious semantic gap within the current MPI standard. For this pur pose, the library offers the programmer additional features that should help to adapt applications to today's hierarchical systems in a convenient and portable way.
A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2(n)-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Expl...
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ISBN:
(纸本)9781424437511
A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2(n)-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Exploiting the features of the MicroBlaze's integrated interfaces instructions are streamed on-demand to the coprocessor to keep the controlflow highly flexible. At the same time the dataflow between hardware and software is minimized. Comparison with previous architectures shows high acceleration of HECC with minor increase in hardware resources. It is demonstrated that this speed-up can be used for countermeasures on algorithmic level against basic side-channel attacks while still keeping real-time constraints.
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