simulation of communication networks is often time consuming. parallelsimulation may be used to reduce the execution time of such a simulator. However, efficient modeling and simulation of such complex applications i...
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ISBN:
(纸本)1565550277
simulation of communication networks is often time consuming. parallelsimulation may be used to reduce the execution time of such a simulator. However, efficient modeling and simulation of such complex applications is not a trivial task. In this paper, we discuss the results of simulating a multigigabit/s network using both an optimistic and a conservative scheme. Our experimental result on a shared memory multiprocessor indicates that the conservative approach is superior to the optimistic one for this application.
Robustness of the simulation mechanism is a requirement for acceptability of distributedsimulation environments. We consider complex and erratic distributed conservative simulations, using colliding pucks as a guidin...
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ISBN:
(纸本)1565550277
Robustness of the simulation mechanism is a requirement for acceptability of distributedsimulation environments. We consider complex and erratic distributed conservative simulations, using colliding pucks as a guiding example. A new mechanism is introduced which allows logical processes to cooperate locally and advance. Advance is made through the collective selection of the next event in a group of logical processes. the algorithm demonstrates scalability through the locality of its determination. A description and proof of correctness is given. the effectiveness of the cooperative acceleration mechanism is illustrated with measurements on road traffic and colliding pucks simulations.
A great deal of research in the area of distributed discrete event simulation has focussed on evaluating the performance of variants of conservative and optimistic methods on different types of applications. Applicati...
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ISBN:
(纸本)1565550277
A great deal of research in the area of distributed discrete event simulation has focussed on evaluating the performance of variants of conservative and optimistic methods on different types of applications. Application characteristics like lookahead, communication patterns, etc. have been found to affect the suitability of a specific protocol to simulate a given model. For many systems, it may be the case that different subsystems possess contradictory characteristics such that whereas some subsystems may be simulated efficiently using a conservative protocol, others may be more amenable to optimistic methods. Furthermore, the suitability of a protocol for a given subsystem may change dynamically. We propose a parallelsimulation protocol that allows different parts of a system to be simulated using different protocols, allowing these protocols to be switched dynamically. A proof of correctness is presented, along with some preliminary performance discussion.
One of the significant difficulties in partitioning logic circuits for distributedsimulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researche...
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ISBN:
(纸本)1565550277
One of the significant difficulties in partitioning logic circuits for distributedsimulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researchers have resorted to pre-simulation to estimate these evaluation frequencies. In this paper we empirically investigate the wisdom of relying on presimulation results, and evaluate the degree to which early evaluation frequencies predict later evaluation frequencies. the results show that, for simulations that use random input vectors, pre-simulation has clear merit in predicting circuit element evaluation frequency. this supports the use of pre-simulation as an input to circuit partitioning algorithms.
Accelerating discrete event simulation can be achieved by using parallel architectures. the use of dedicated hardware is a possible alternative in some special domains like logic simulation. However, few studies have ...
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ISBN:
(纸本)1565550277
Accelerating discrete event simulation can be achieved by using parallel architectures. the use of dedicated hardware is a possible alternative in some special domains like logic simulation. However, few studies have focused on general *** paper presents an innovative solution using a recent hardware technology called FPGA (Field Programmable Gate Array), that enables dynamic synthesis of application specific hardware. Each node of an MIMD parallel machine is tightly coupled to an FPGA ring. this ring allows us to synthesize application specific global operatorsand control or communication circuits and complements the possibilities of the original machine on a wide application spectrum. We present the first results obtained in the simulation field with an eight node prototype.
In this contribution an implemented prototype of an object server on a parallel computer is described. In the first phase a model iras been proposed and simulated in Ada'95. Based on obtained experiences with run-...
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ISBN:
(纸本)0818681489
In this contribution an implemented prototype of an object server on a parallel computer is described. In the first phase a model iras been proposed and simulated in Ada'95. Based on obtained experiences with run-time features of the simulation program a corresponding prototype has been implemented in C++, tested, and the obtained results have been compared with results of the simulation.
In Time Warp optimistic discrete event simulation, there exists a need to occasionally save the states of the logical processes. the state saving often constitutes a substantial overhead. However it is not necessary t...
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ISBN:
(纸本)1565550277
In Time Warp optimistic discrete event simulation, there exists a need to occasionally save the states of the logical processes. the state saving often constitutes a substantial overhead. However it is not necessary to save each state of a logical process since states can be restored from earlier states by re-executing intermediate events. In this paper, we analyse the effects of doing the state saving less frequently and present a method that allows each logical process to adapt its state saving interval to its rollback behaviour. Experimental results indicate that the proposed method improves performance of the Time Warp system.
In this paper we discuss the application of domain decomposition methods to circuit simulation. this coarse grain parallelization guarantees a minimum of communication and thus achieves good speedup results on a works...
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ISBN:
(纸本)1565550277
In this paper we discuss the application of domain decomposition methods to circuit simulation. this coarse grain parallelization guarantees a minimum of communication and thus achieves good speedup results on a workstation cluster. Our results show that with a cluster of ten powerful RISC workstations comparable turn around times to a supercomputer can be achieved. Furthermore a workstation cluster offers the possibility to simulate electric circuits with a size of new magnitude. On a cluster of 27 workstations we succeeded in simulating a circuit with 135000 transistors, while we failed to simulate the same circuit on our supercomputer because of a lack of memory.
this paper describes a tool, LAPSE (Large Application parallelsimulation Environment), that allows one to use a small number of parallel processors to simulate the behavior of a message-passing code running on a larg...
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ISBN:
(纸本)1565550277
this paper describes a tool, LAPSE (Large Application parallelsimulation Environment), that allows one to use a small number of parallel processors to simulate the behavior of a message-passing code running on a large number of processors, for the purposes of scalability studies and performance tuning. LAPSE is implemented on the Intel Paragon, and has achieved small slowdowns (relative to native code) and high speed-ups on large problems.
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