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检索条件"任意字段=Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays, FPGA"

共 13982 条记录，以下是51-60 订阅

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Invited: Innovation in Times of Technology Disruption 25

Invited: Innovation in Times of Technology Disruption

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proceedings of the 2025 international symposium on Physical Design

作者： Bryan Preas Technology Consulting Battle Ground WA USA

ISBN: (纸本)9798400712937

I hosted Jason Cong when he was an intern at the Xerox Palo Alto Research Center in 1987. Since then, we have been friends and collaborators. I have watched his extraordinary accomplishments with pride and pleasure over the *** technologies are a well-studied business school topic. New, or significantly improved, technologies present new problems and allow new approaches for older challenges. These disruptions are often accompanied by substantial technical innovation and creation of new business values. In their time, electric power, automobiles and television disrupted society. More recent examples include the internet and e-commerce.

关键词： field programmable gate array

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OLAF′16: Second international Workshop on Overlay Architectures for fpgas 16

OLAF′16: Second International Workshop on Overlay Architect...

引用

acm/SIGDA international symposium on field-programmable gate arrays (fpga)

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450338561

The Second international Workshop on Overlay Architectures for fpgas is held in Monterey, California, USA, on February 21, 2016 and co-located with fpga 2016: The 24th acm/SIGDA international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by fpga-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in fpga overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.

关键词： fpga Overlay architecture

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Acceleration of Graph Neural Networks with Heterogenous Accelerators Architecture 24

Acceleration of Graph Neural Networks with Heterogenous Acce...

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proceedings of the SC '24 Workshops of the international Conference on High Performance Computing, Network, Storage, and Analysis

作者： Kaiwen Cao Archit Gajjar Liad Gerstman Kun Wu Sai Rahul Chalamalasetti Aditya Dhakal Giacomo Pedretti Pavana Prakash Wen-mei Hwu Deming Chen Dejan Milojicic University of Illinois Urbana-Champaign and Hewlett Packard Labs Hewlett Packard Labs Technion-Israel Institute of Technology University of Illinois Urbana-Champaign d-Matrix and Hewlett Packard Labs University of Illinois Urbana-Champaign and Nvidia

ISBN: (纸本)9798350355543

Graph Neural Networks (GNNs) have been used to solve complex problems of drug discovery, social media analysis, etc. Meanwhile, GPUs are becoming dominating accelerators to improve deep neural network performance. However, due to the characteristics of graph data, it is challenging to accelerate GNN-type workloads with GPUs alone. GraphSAGE is one representative GNN workload that uses sampling to improve GNN learning efficiency. Profiling the GraphSAGE using PyG library reveals that the sampling stage on the CPU is the bottleneck. Hence, we propose a heterogeneous system architecture solution with the sampling algorithm accelerated on customizable accelerators (fpga), and feed sampled data into GPU training through a PCIe Peer-to-Peer (P2P) communication flow. With fpga acceleration, for the sampling stage alone, we achieve a speed-up of 2.38 × to 8.55 × compared with sampling on CPU. For end-to-end latency, compared with the traditional flow, we achieve a speed-up of 1.24 × to 1.99 ×.

关键词： field programmable gate Array (fpga)

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OLAF′17: Third international Workshop on Overlay Architectures for fpgas 17

OLAF′17: Third International Workshop on Overlay Architectu...

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acm/SIGDA international symposium on field-programmable gate arrays

作者： So, Hayden Kwok-Hay Wawrzynek, John Univ Hong Kong Dept Elect & Elect Engn Hong Kong Peoples R China Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781450343541

The Third international Workshop on Overlay Architectures for fpgas (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with fpga 2017: The 25th acm/SIGDA international symposium on field programmable gate arrays. The main objective of the workshop is to address how overlay architectures can help address the challenges and opportunites provided by fpga-based reconfigurable computing. The workshop provides a venue for researchers to present and discuss the latest developments in fpga overlay architecture and related areas. We have assembled a program of six refereed papers with panel discussions with prominent experts in the field.

关键词： fpga Overlay architecture

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

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IEEE symposium on High-Performance Computer Architecture

作者： Jiaqi Zhai Xuanhua Shi Kaiyi Huang Chencheng Ye Weifang Hu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computing National University of Singapore Singapore

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art fpga, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication.

关键词： Quantization (signal) High dimensional data Memory management Graphics processing units Bandwidth Real-time systems Sparse matrices Recommender systems field programmable gate arrays Optimization

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Architectural Improvements for field programmable Counter arrays: Enabling Efficient Synthesis of Fast Compressor Trees on fpgas 08

Architectural Improvements for Field Programmable Counter Ar...

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16th acm/SIGDA international symposium on field-programmable gate arrays

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Brisk, Philip Gurkaynak, Frank K. Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Inst Microelect & Microsyst Microelect Syst Lab CH-1015 Lausanne Switzerland

ISBN: (纸本)9781595939340

The field programmable Counter Array (FPCA) was introduced to improve fpga performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an fpga. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA;the remaining portion of the circuit is synthesized on the fpga. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an fpga containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks.

关键词： fpga field programmable Counter Array (FPCA)

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EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform

EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platf...

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IEEE symposium on High-Performance Computer Architecture

作者： Yi Huang Xinsheng Gong Xiangyu Kong Dibei Chen Jianfeng Zhu Wenping Zhu Liangwei Li Mingyu Gao Shaojun Wei Aoyang Zhang Leibo Liu Tsinghua University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Fully Homomorphic Encryption (FHE) is a set of powerful cryptographic schemes that allows computation to be performed directly on encrypted data with an unlimited depth. Despite FHE’s promising in privacy-preserving computing, yet in most FHE schemes, ciphertext generally blows up thousands of times compared to the original message, and the massive amount of data load from off-chip memory for bootstrapping and privacy-preserving machine learning applications (such as HELR, ResNet-20), both degrade the performance of FHE-based computation. Several hardware designs have been proposed to address this issue, however, most of them require enormous resources and power. An acceleration platform with easy programmability, high efficiency, and low overhead is a prerequisite for practical application. This paper proposes EFFACT, a highly efficient full-stack FHE acceleration platform with a compiler that provides comprehensive optimizations and vector-friendly hardware. We start by examining the computational overhead across different real-world benchmarks to highlight the potential benefits of reallocating computing resources for efficiency enhancement. Then we make a design space exploration to find an optimal SRAM size with high utilization and low cost. On the other hand, EFFACT features a novel optimization named streaming memory access which is proposed to enable high throughput with limited SRAMs. Regarding the software-side optimization, we also propose a circuit-level function unit reuse scheme, to substantially reduce the computing resources without performance degradation. Moreover, we design novel NTT and automorphism units that are suitable for a cost-sensitive and highly efficient architecture, leading to low area. For generality, EFFACT is also equipped with an ISA and a compiler backend that can support several FHE schemes like CKKS, BGV, and BFV. We provide both fpga and ASIC versions of EFFACT. On account of our full stack design, fpga-EFFACT outperforms the

关键词： Costs Memory management Random access memory Benchmark testing Throughput Hardware Space exploration Cryptography Optimization field programmable gate arrays

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Network-on-Chip programmable Platform in Versal™ ACAP Architecture

Network-on-Chip Programmable Platform in Versal™ ACAP Archi...

引用

acm/SIGDA international symposium on field-programmable gate arrays (fpga)

作者： Swarbrick, Ian Gaitonde, Dinesh Ahmad, Sagheer Gaide, Brian Arbel, Ygal Xilinx Inc San Jose CA 95124 USA

ISBN: (纸本)9781450361378

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal (TM) architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in fpga devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, fpga fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

关键词： ACAP Versal fpga Stacked Silicon SSIT Adaptable Compute Acceleration Platform NoC fpga Architecture fpga CAD Xilinx

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High-Performance QR Decomposition for fpgas 18

High-Performance QR Decomposition for FPGAs

引用

acm/SIGDA international symposium on field-programmable gate arrays (fpga)

作者： Langhammer, Martin Pasca, Bogdan Intel Programmable Solut Grp Swindon Wilts England Intel Programmable Solut Grp Paris France

ISBN: (纸本)9781450356145

QR decomposition (QRD) is of increasing importance for many current applications, such as wireless and radar. Data dependencies in known algorithms and approaches, combined with the data access patterns used in many of these methods, restrict the achievable performance in software programmable targets. Some fpga architectures now incorporate hard floating-point (HFP) resources, and in combination with distributed memories, as well as the flexibility of internal connectivity, can support high-performance matrix arithmetic. In this work, we present the mapping to parallel structures with inter-vector connectivity of a new QRD algorithm. Based on a Modified Gram-Schmidt (MGS) algorithm, this new algorithm has a different loop organization, but the dependent functional sequences are unchanged, so error analysis and numerical stability are unaffected. This work has a theoretical sustained-to-peak performance close to 100% for large matrices, which is roughly three times the functional density of the previously best known implementations. Mapped to an Intel Arria 10 device, we achieve 80us for a 256x256 single precision real matrix, for a 417 GFLOP equivalent. This corresponds to a 95% sustained to peak ratio, for the portion of the device used for this work.

关键词： QRD MGS fpga Arria10 throughput

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AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Ne...

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IEEE symposium on High-Performance Computer Architecture

作者： Liyan Chen Dongxu Lyu Jianfei Jiang Qin Wang Zhigang Mao Naifeng Jing Department of Micro/Nano Electronics Shanghai Jiao Tong University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

DIMM-based near-memory processing (NMP) architectures address the “memory wall” problem by incorporating near-memory accelerators (NMAs) into main memory devices for high memory bandwidth and low energy consumption. However, critical challenges prevent efficient asynchronous execution between host and NMAs in DIMM-NMP architectures. Memory controllers (MCs) distributed at the host side and the NMA side issue memory accesses independently without synchronization on memory states, which may lead to memory bus contention and DRAM errors. Therefore, most existing DIMM-NMP designs adopt synchronous execution to prevent concurrent memory accesses. However, this intervention wastes either the host or the NMA computation capability. In this work, we propose AsyncDIMM, a novel DIMM-NMP design with efficient asynchronous execution based on existing memory buses. It enables single access mode (host or NMA), concurrent access mode, and a seamless switch between them. First, we propose the offload-schedule-return mechanism with explicit and implicit synchronization to ensure memory access correctness for all memory modes. Second, to further improve bandwidth utilization and decrease access latency, we introduce optimized timing constraints for offloading, a locality-aware switch-recovery method for scheduling, and adaptive batch with timing-division multiplexing notification for returning. Finally, we present a detailed design with limited hardware modifications to conventional host and NMA MCs, which is extensively validated on the fpga. Comprehensive experiments demonstrate that AsyncDIMM outperforms four NMP baselines by $1.19 \times-1.92 \times$, enabling efficient asynchronous execution with up to $2.25 \times$ bandwidth utilization uplift and 47% access latency reduction.

关键词： Multiplexing Energy consumption Memory management Memory architecture Random access memory Bandwidth Switches Hardware Synchronization field programmable gate arrays

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