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检索条件"任意字段=Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation"

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The nesC language:: A holistic approach to networked embedded systems 03

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conference on programming language design and implementation

作者： Gay, D Levis, P von Behren, R Welsh, M Brewer, E Culler, D Univ Calif Berkeley EECS Dept Berkeley CA 94720 USA Intel Res Berkeley Berkeley CA 94704 USA

ISBN: (纸本)9781581136623

We present nesC, a programming language for networked embedded systems that represent a new design space for application developers. An example of a networked embedded system is a sensor network, which consists of (potentially) thousands of tiny, low-power "motes," each of which execute concurrent, reactive programs that must operate with severe memory and power constraints. nesC's contribution is to support the special needs of this domain by exposing a programming model that incorporates event-driven execution, a flexible concurrency model, and component-oriented application design. Restrictions on the programming model allow the nesC compiler to perform whole-program analyses, including data-race detection (which improves reliability) and aggressive function inlining (which reduces resource consumption). nesC has been used to implement TinyOS, a small operating system for sensor networks, as well as several significant sensor applications. nesC and TinyOS have been adopted by a large number of sensor network research groups, and our experience and evaluation of the language shows that it is effective at supporting the complex, concurrent programming style demanded by this new class of deeply networked systems.

关键词： programming languages C concurrency data races components modules first-order nesC TinyOS

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Static array storage optimization in MATLAB 03

引用

conference on programming language design and implementation

作者： Joisha, PG Banerjee, P Northwestern Univ ECE Dept Evanston IL 60208 USA

ISBN: (纸本)9781581136623

An adaptation of the classic register allocation algorithm to the problem of array storage optimization in MATLAB is presented. The method involves the decomposition of an interference graph's color classes using inferred type information. A key trait is the use of symbolic types, along with control flow, in performing the decomposition. On a benchmark suite spanning the published test suites of some recent research MATLAB compilers, our implementation produces savings in the average virtual memory size, with respect to code generated by a commercial MATLAB compiler, of between 51% and 139% in 6 out of 11 programs, and savings between 0.7% and 47% in the remaining. In absolute terms, this ranged from 123KB to over 9MB. Substantial improvements in other categories of memory, such as resident sets and dynamic data (stack plus heap), were also observed and are reported. Speedups in execution times of at least over an order of magnitude in 4 programs, of over 100% in 4 of the remaining, and 10% and over in-the rest are also reported.

关键词： algorithms design languages performance

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Linear analysis and optimization of stream programs 03

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conference on programming language design and implementation

作者： Lamb, AA Thies, W Amarasinghe, S MIT Comp Sci Lab Cambridge MA 02139 USA

ISBN: (纸本)9781581136623

As more complex DSP algorithms are realized in practice, there is an increasing need for high-level stream abstractions that can be compiled without sacrificing efficiency. Toward this end, we present a set of aggressive optimizations that target linear sections of a stream program. Our input language is StreamIt, which represents programs as a hierarchical graph of autonomous filters. A filter is linear if each of its outputs can be represented as an affine combination of its inputs. Linearity is common in DSP components;examples include FIR filters, expanders, compressors, FFTs and DCTs. We demonstrate that several algorithmic transformations, traditionally hand-tuned by DSP experts, can be completely automated by the compiler. First, we present a linear extraction analysis that automatically detects linear filters from the C-like code in their work function. Then, we give a procedure for combining adjacent linear filters into a single filter, as well as for translating a linear filter to operate in the frequency domain. We also present an optimization selection algorithm, which finds the sequence of combination and frequency transformations that will give the maximal benefit. We have completed a fully-automatic implementation of the above techniques as part of the StreamIt compiler, and we demonstrate a 450% performance improvement over our benchmark suite.

关键词： stream programming streamIt optimization embedded linear systems algebraic simplification DSP FFT

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A provably sound TAL for back-end optimization 03

引用

conference on programming language design and implementation

作者： Chen, J Wu, DH Appel, AW Fang, H Princeton Univ Princeton NJ 08544 USA Yale Univ New Haven CT 06520 USA

ISBN: (纸本)9781581136623

Typed assembly languages provide a way to generate machine-checkable safety proofs for machine-language programs. But the soundness proofs of most existing typed assembly languages are hand-written and cannot be machine-checked, which is worrisome for such large calculi. We have designed and implemented a low-level typed assembly language (LTAL) with a semantic model and established its soundness from the model. Compared to existing typed assembly languages, LTAL is more scalable and more secure;it has no macro instructions that hinder low-level optimizations such as instruction scheduling;its type constructors are expressive enough to capture dataflow information, support the compiler's choice of data representations and permit typed position-independent code;and its type-checking algorithm is completely syntax-directed. We have built a prototype system, based on Standard ML of New Jersey, that compiles most of core ML to Sparc code. We explain how we were able to make the untyped back end in SML/NJ preserve types during instruction selection and register allocation, without restricting low-level optimizations and without knowledge of any type system pervading the instruction selector and register allocator.

关键词： languages verification typed assembly language proof-carrying code

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Stride prefetching by dynamically inspecting objects

Stride prefetching by dynamically inspecting objects

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conference on programming language design and implementation

作者： Inagaki, T Onodera, T Komatsu, H Nakatani, T IBM Japan Ltd Tokyo Res Lab Yamato Kanagawa 2428502 Japan

Software prefetching is a promising technique to hide cache miss latencies, but it remains challenging to effectively prefetch pointer-based data structures because obtaining the memory address to be prefetched requires pointer dereferences. The recently proposed stride prefetching overcomes this problem, but it only exploits inter-iteration stride patterns and relies on an off-line profiling method. We propose a new algorithm for stride prefetching which is intended for use in a dynamic compiler. We exploit both inter- and intra-iteration stride patterns, which we discover using an ultra-lightweight profiling technique, called object inspection. This is a kind of partial interpretation that only a dynamic compiler can perform. During the compilation of a method, the dynamic compiler gathers the profile information by partially interpreting the method using the actual values of parameters and causing no side effects. We evaluated an implementation of our prefetching algorithm in a production-level Java just-in-time compiler. The results show that the algorithm achieved up to an 18.9% and 25.1% speedup in industry-standard benchmarks on the Pentium 4 and the Athlon MP, respectively, while it increased the compilation time by less than 3.0%.

关键词： algorithm design experimentation performance Java just-in-time compiler object-inspection stride prefetching

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A static analyzer for large safety-critical software 03

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conference on programming language design and implementation

作者： Blanchet, B Cousot, P Cousot, R Feret, J Mauborgne, L Miné, A Monniaux, D Rival, X CNRS F-75700 Paris France Ecole Normale Super Paris France Ecole Polytech F-91128 Palaiseau France

ISBN: (纸本)9781581136623

We show that abstract interpretation-based static program analysis can be made efficient and precise enough to formally verify a class of properties for a family of large programs with few or no false alarms. This is achieved by refinement of a general purpose static analyzer and later adaptation to particular programs of the family by the end-user through parametrization. This is applied to the proof of soundness of data manipulation operations at the machine level for periodic synchronous safety critical embedded software. The main novelties are the design principle of static analyzers by refinement and adaptation through parametrization (Sect. 3 and 7), the symbolic manipulation of expressions to improve the precision of abstract transfer functions (Sect. 6.3), the octagon (Sect. 6.2.2), ellipsoid (Sect. 6.2.3), and decision tree (Sect. 6.2.4) abstract domains, all with sound handling of rounding errors in floating point computations, widening strategies (with thresholds: Sect. 7.1.2, delayed: Sect. 7.1.3) and the automatic determination of the parameters (parametrized packing: Sect. 7.2).

关键词： algorithms design experimentation reliability theory verification abstract interpretation abstract domains static analysis verification floating point embedded reactive real-time safety-critical software

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Meta optimization: Improving compiler heuristics with machine learning 03

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conference on programming language design and implementation

作者： Stephenson, M Amarasinghe, S Martin, M O'Reilly, UM MIT Comp Sci Lab Cambridge MA 02139 USA MIT Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781581136623

Compiler writers have crafted many heuristics over the years to approximately solve NP-hard problems efficiently. Finding a heuristic that performs well on a broad range of applications is a tedious and difficult process. This paper introduces Meta Optimization, a methodology for automatically fine-tuning compiler heuristics. Meta Optimization uses machine-learning techniques to automatically search the space of compiler heuristics. Our techniques reduce compiler design complexity by relieving compiler writers of the tedium of heuristic tuning. Our machine-learning system uses an evolutionary algorithm to automatically find effective compiler heuristics. We present promising experimental results. In one mode of operation Meta Optimization creates application-specific heuristics which often result in impressive speedups. For hyperblock formation, one optimization we present in this paper, we obtain an average speedup of 23% (up to 73%) for the applications in our suite. Furthermore, by evolving a compiler's heuristic over several benchmarks, we can create effective, general-purpose heuristics. The best general-purpose heuristic our system found for hyperblock formation improved performance by an average of 25% on our training set, and 9% on a completely unrelated test set. We demonstrate the efficacy of our techniques - on three different optimizations in this paper: hyperblock formation, register allocation, and data prefetching.

关键词： machine learning priority functions genetic programming compiler heuristics

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A region-based compilation technique for a Java just-in-time compiler 03

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conference on programming language design and implementation

作者： Suganuma, T Yasue, T Nakatani, T IBM Japan Ltd Tokyo Res Lab Yamato 2428502 Japan

ISBN: (纸本)9781581136623

Method inlining and data flow analysis are two major optimization components for effective program transformations, however they often suffer from the existence of rarely or never executed code contained in the target method. One major problem lies in the assumption that the compilation unit is partitioned at method boundaries. This paper describes the design and implementation of a region-based compilation technique in our dynamic compilation system, in which the compiled regions are selected as code portions without rarely executed code. The key part of this technique is the region selection, partial inlining, and region exit handling. For region selection, we employ both static heuristics and dynamic profiles to identify rare sections of code. The region selection process and method inlining decision are interwoven, so that method inlining exposes other targets for region selection, while the region selection in the inline target conserves the inlining budget, leading to more method inlining. Thus the inlining process can be performed for parts of a method, not for the entire body of the method. When the program attempts to exit from a region boundary, we trigger recompilation and then rely on on-stack replacement to continue the execution from the corresponding entry point in the recompiled code. We have implemented these techniques in our Java JIT compiler, and conducted a comprehensive evaluation. The experimental results show that the approach of region-based compilation achieves approximately 5% performance improvement on average, while reducing the compilation overhead by 20 to 30%, in comparison to the traditional function-based compilation techniques.

关键词： performance design experimentation measurement languages region-based compilation dynamic compilers partial inlining on-stack replacement

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A compiler framework for speculative analysis and optimizations 03

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conference on programming language design and implementation

作者： Lin, J Chen, T Hsu, WC Ju, RDC Ngai, TF Yew, PC Chan, S Univ Minnesota Dept Comp Sci & Engn Minneapolis MN 55455 USA Intel Corp Microproc Res Lab Santa Clara CA 95052 USA

ISBN: (纸本)9781581136623

Speculative execution, such as control speculation and data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristic rules, existing compiler frameworks can adequately incorporate and exploit control speculation. However, very little has been done so far to allow existing compiler frameworks to incorporate and exploit data speculation effectively in various program transformations beyond instruction scheduling. This paper proposes a speculative SSA form to incorporate information from alias profiling and/or heuristic rules for data speculation, thus allowing existing program analysis frameworks to be easily extended to support both control and data speculation. Such a general framework is very useful for EPIC architectures that provide checking (such as advanced load address table (ALAT) [10]) on data speculation to guarantee the correctness of program execution. We use SSAPRE [2 1] as one example to illustrate how to incorporate data speculation in those important compiler optimizations such as partial redundancy elimination (PRE), register promotion, strength reduction and linear function test replacement. Our extended framework allows both control and data speculation to be performed on top of SSAPRE and, thus, enables more aggressive speculative optimizations. The proposed framework has been implemented on Intel's Open Research Compiler (ORC). We present experimental data on some SPEC2000 benchmark programs to demonstrate the usefulness of this framework and how data speculation benefits partial redundancy elimination.

关键词： algorithms performance design experimentation speculative SSA form speculative weak update data speculation partial redundancy elimination register promotion

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Compile-time dynamic voltage scaling settings: Opportunities and limits 03

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conference on programming language design and implementation

作者： Xie, F Martonosi, M Malik, S Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9781581136623

With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-time power-management techniques, dynamic voltage scaling (DVS) has emerged as an important approach, with the ability to provide significant power savings. DVS exploits the ability to control the power consumption by varying a processor's supply voltage (V) and clock frequency (f). DVS controls energy by scheduling different parts of the computation to different (V, f) pairs;the goal is to minimize energy while meeting performance needs. Although processors like the Intel XScale and Transmeta Crusoe allow software DVS control, such control has thus far largely been used at the process/task level under operating system control. This is mainly because the energy and time overhead for switching DVS modes is considered too large and difficult to manage within a single program. In this paper we explore the opportunities and limits of compile-time DVS scheduling. We derive an analytical model for the maximum energy savings that can be obtained using DVS given a few known program and processor parameters. We use this model to determine scenarios where energy consumption benefits from compile-time DVS and those where there is no benefit. The model helps us extrapolate the benefits of compile-time DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through optimal settings of DVS modes. This is done by extending the existing Mixed-integer Linear Program (MILP) formulation for this problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical

关键词： low power compiler dynamic voltage scaling Mixed-Integer Linear programming analytical model

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