In the context of sequential computers, it is common practice to exploit temporal locality of reference through devices such as caches and virtual memory. In the context of multiprocessors, we believe that it is equal...
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In the context of sequential computers, it is common practice to exploit temporal locality of reference through devices such as caches and virtual memory. In the context of multiprocessors, we believe that it is equally important to exploit spatial locality of reference. We are developing a system which, given a sequential program and its domain decomposition, performs process decomposition so as to enhance spatial locality of reference. We describe an application of this method - generating code from shared-memory programs for the (distributed memory) Intel iPSC/2.
作者:
Kim, Ju-WhanNam, Tek-JinCIDR Lab
Department of Industrial Design KAIST 291 Daehak-ro Yuseong-gu Daejeon 305-701 Korea Republic of
Prototyping of gestural interactions in the early phase of design is one of the most challenging tasks for designers without advanced programming skills. Relating users' input from gesture-based sensor values requ...
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In this paper, we present a technique for summarizing the data accesses in a given region and show how this summary can be used to detect and enhance task parallelism in a program. For the sake of simplicity, we restr...
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In this paper, we present a technique for summarizing the data accesses in a given region and show how this summary can be used to detect and enhance task parallelism in a program. For the sake of simplicity, we restrict our discussion to Fortran programs that consist of a sequence of perfectly-nested loops in which all subroutine calls are expanded inline. However, the techniques presented here can easily be extended to the general case of programs with imperfectly nested loops and subroutine calls.
Live programming allows programmers to edit the code of a running program and immediately see the effect of the code changes. This tightening of the traditional edit-compile-run cycle reduces the cognitive gap between...
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ISBN:
(纸本)9781450320146
Live programming allows programmers to edit the code of a running program and immediately see the effect of the code changes. This tightening of the traditional edit-compile-run cycle reduces the cognitive gap between program code and execution, improving the learning experience of beginning programmers while boosting the productivity of seasoned ones. Unfortunately, live programming is difficult to realize in practice as imperative languages lack well-defined abstraction boundaries that make live programming responsive or its feedback comprehensible. This paper enables live programming for user interface programming by cleanly separating the rendering and non-rendering aspects of a UI program, allowing the display to be refreshed on a code change without restarting the program. A type and effect system formalizes this separation and provides an evaluation model that incorporates the code update step. By putting live programming on a more formal footing, we hope to enable critical and technical discussion of live programming systems.
A Petri net is a graphical and mathematical modeling tool useful in the analysis of concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic systems. In addition, interest in Petri nets is ...
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ISBN:
(纸本)0897914775
A Petri net is a graphical and mathematical modeling tool useful in the analysis of concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic systems. In addition, interest in Petri nets is increasing in the software community to model the behavior of parallel computer programs. The introduction of timed Petri nets allows system or program performance to be estimated as well. This paper begins with a general discussion, including definitions, for both ordinary and timed Petri nets. Several analysis tools are outlined for ordinary and timed Petri nets including analysis of the incidence matrix, coverability tree, firing diagram, and the GRID (Graph of Reachable Instantaneous Descriptions). This paper then introduces a method for representing Petri nets in APL2 and defines an easy input method. An APL2 implementation of each of the above analysis tools is given. These functions are described in detail as to their operation. Several examples of their use are given including examples of deadlock detection and performance estimation.
This paper reports on experimental results which demonstrate the potential of Ada as a parallel programminglanguage for large scale, scientific applications on high performance multiprocessors. Reported performance r...
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Dynamically-typed object-oriented languages please programmers, but their lack of static type information penalizes performance. Our new implementation techniques extract static type information from declaration-free ...
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Dynamically-typed object-oriented languages please programmers, but their lack of static type information penalizes performance. Our new implementation techniques extract static type information from declaration-free programs. Our system compliles several copies of a given procedure, each customized for one receiver type, so that the type of the receiver is bound at compile time. The compiler predicts types that are statically unknown but likely, and inserts run-time type tests to verify its predictions. It splits calls, compiling a copy on each control path, optimized to the specific types on that path. Coupling these new techniques with compile-time message lookup, aggressive procedure inlining, and traditional optimizations has doubled the performance of dynamically-typed object-oriented languages.
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware d...
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ISBN:
(纸本)0769514413
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually, this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.
This paper deals with the use of APL to solve matrix theory problems with elements that are members of an integral domain. Two types of integral domains are used to illustrate the methods developed in this paper, inte...
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ISBN:
(纸本)0897914775
This paper deals with the use of APL to solve matrix theory problems with elements that are members of an integral domain. Two types of integral domains are used to illustrate the methods developed in this paper, integers (Z) and polynomials with real coefficients (Re[X]). However, the method of approach can be easily generalized to include other integral domains. APL2, due to its generalized data representations and rich functional semantics, was chosen to implement the solution to this problem. For each integral domain presented, a method of data representation is developed, and implementations of the necessary `primitive' functions (Addition, Multiplication, Division, and Comparison) are given. Finally, this newly developed system of functions and data representation is used to solve several of the most common Matrix Algebra problems. A simple recursive determinant and an implementation of Euclid's Greatest Common Divisor Algorithm are presented. Then, with these building blocks, a general algorithm for finding Smith's Canonical form and an algorithm to find the Invariant Factors are presented.
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover;they are frequently on a to...
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ISBN:
(纸本)0769500137
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover;they are frequently on a too high abstraction level to allow for efficient synthesis with today's techniques. We address this problem with a modelling method, which is strictly formal and based on formal semantics, a pure functional language, and the synchrony hypothesis. But the use of skeletons in conjunction with a proper computational model allows to associate a direct hardware interpretation. In particular we use (1) the synchrony hypothesis and a timed signal model to provide a high abstraction for communication at the system level. This facilitates efficient modelling and design space exploration at the functional level, because the designer is Hot concerned with complex communication mechanisms, mid functionality can easily be moved front one block to another: To bridge the gap bent een an elegant and abstract functional model and the details of an implementation we use (2) skeletons to encapsulate primitive structures, such as FSMs, buffers, computation units, etc, irt a purely functional way.
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