The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optim...
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The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optimization are both desirable and feasible, since the added execution time is a small fraction of the total optimization time. The implementation of a resource sharing system called ISIS, which uses bit-level modeling, accounts for control delays, and optimizes sharing and resource performance selection together to generate high-quality circuits from register transfer language (RTL) descriptions, is described.< >
It is shown that object-oriented designs requiring inheritance and run-time polymorphism can be implemented in Ada. A technique for specifying object classes and relationships is described. Package specifications and ...
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It is shown that object-oriented designs requiring inheritance and run-time polymorphism can be implemented in Ada. A technique for specifying object classes and relationships is described. Package specifications and subprogram stubs that implement the specified system are automatically generated; the programmer only writes the actual method implementation bodies. The technique presented is an application of the principles presented by P. Baker (1990). Ada is used as a preprocessing language, providing two levels of checking by the compiler. The OOP (object-oriented programming) programmer writes two Ada package specifications and a main program (procedure). One package provides the names of types, classes, and methods that will be used by the object system; the other provides information about the types that are to be declared. The main program specifies methods, classes, inheritance structures, and structures for dealing with polymorphism.< >
EZ is a system that integrates traditional operating systems and programminglanguages into a very-high-level persistent string processing language. The authors describe the design and initial implementation of a dist...
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EZ is a system that integrates traditional operating systems and programminglanguages into a very-high-level persistent string processing language. The authors describe the design and initial implementation of a distributed memory manager that distributes EZ's virtual address space transparently among a network of homogeneous computers. The design adapts the techniques used in recent implementation of shared virtual memory for use in EZ's persistent environment. Unlike most implementations of shared virtual memory, control information is distributed and migrates. This memory manager works in concert with a distributed mark-and-sweep garbage collector, which is also concurrent and real-time. This collector trades time for space and minimal disruption of mutators, which reduces communication costs.< >
The authors describe a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant machine is derived from a hierarchy of...
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The authors describe a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant machine is derived from a hierarchy of sub-machine descriptions, each represented by a production. The production-based specification (PBS) consists of productions annotated with HDL action code, and forms the input to a design tool which outputs procedural HDL tailored for hardware synthesis. Due to the concise nature of this form of specification, the technique can save enormous labor in the construction of procedural specifications for these machines. Novel aspects of this research include the compilation of a PBS with HDL action clauses into synthesizable procedural HDL and the approach to specification of machine behavior in the event of exceptional conditions.< >
This paper discusses the requirement for intermachine communication and how this requirement is met with APL2's cross-system shared variables. One problem encountered in the design is the mapping of APL2's coo...
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ISBN:
(纸本)0897914775
This paper discusses the requirement for intermachine communication and how this requirement is met with APL2's cross-system shared variables. One problem encountered in the design is the mapping of APL2's cooperative peer-to-peer communication model onto a client server data transport mechanism. Another is the ability of APL2's sharing mechanism to address applications on other machines. The goal of the facility is to provide a high level of communication between applications running on different machines while introducing the minimum language extension.
Tachyon Common Lisp is an efficient and portable implementation of Common Lisp 2nd Edition. The design objective of Tachyon is to apply both advanced optimization technology developed for RISC processors and Lisp opt...
ISBN:
(纸本)9780897914819
Tachyon Common Lisp is an efficient and portable implementation of Common Lisp 2nd Edition. The design objective of Tachyon is to apply both advanced optimization technology developed for RISC processors and Lisp optimization techniques. The compiler generates very fast codes comparable to, and sometimes faster than the code generated by UNIX C compiler. Comparing with the most widely used commercial Common Lisp, Tachyon Common Lisp compiled code is 2 times faster and the interpreter is 6 times faster than the Lisp in Gabriel benchmark suit. Tachyon Common Lisp is the fastest among the Lisp systems known to the authors.
This research is conducted as part of the Business Class European project. The aim of the project is to promote object-oriented software development within the framework of management information systems. The Business...
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This research is conducted as part of the Business Class European project. The aim of the project is to promote object-oriented software development within the framework of management information systems. The Business Class development method is supported by an analysis workbench based on the O* method and a design workbench dedicated to the Eiffel language. The communication presents a set of mapping rules from O* specifications to an Eiffel implementation. The practical results as well as the mismatch difficulties can be translated to other object-oriented methods and languages.< >
The authors describe the major aspects in their transputer-based automatic vision system (TAVS) aiming to implement a scaleable and easily reconfigurable system, in which the mapping of image processing and recognitio...
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The authors describe the major aspects in their transputer-based automatic vision system (TAVS) aiming to implement a scaleable and easily reconfigurable system, in which the mapping of image processing and recognition algorithms to the hardware is facilitated by automatic code generation schemes, separating methodic design and implementation details. The paper presents the system design and underlying hardware architecture first. The authors describe the modules available for iconic image processing and feature extraction and selection. The code generation for the hierarchical statistical decision network is then described, followed by the implementation of the language pi for process allocation. The various system parts were tested in an implementation of real-time wooden board inspection. For this example the authors present details on typical algorithms and how they were implemented on a maintainable and scaleable industrial system.< >
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