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检索条件"任意字段=Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation"

共 1226 条记录，以下是361-370 订阅

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And Then There Were None: A Stall-Free Real-Time Garbage Collector for Reconfigurable Hardware 12

And Then There Were None: A Stall-Free Real-Time Garbage Col...

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33rd acm sigplan conference on programming language design and implementation

作者： Bacon, David F. Cheng, Perry Shukla, Sunil IBM Research Hawthorne NY USA

ISBN: (纸本)9781450312059

Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection. We present the first implementation of a complete garbage collector in hardware (as opposed to previous "hardware-assist" techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%. We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.

关键词： design languages Experimentation Performance Block RAM FPGA High Level Synthesis Garbage Collection Real Time

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programming with Binders and Indexed Data-Types 12

Programming with Binders and Indexed Data-Types

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39th Annual acm sigplan-SIGACT Symposium on Principles of programming languages

作者： Cave, Andrew Pientka, Brigitte McGill Univ Montreal PQ H3A 2T5 Canada

ISBN: (纸本)9781450310833

We show how to combine a general purpose type system for an existing language with support for programming with binders and contexts by refining the type system of ML with a restricted form of dependent types where index objects are drawn from contextual LF. This allows the user to specify formal systems within the logical framework LF and index ML types with contextual LF objects. Our language design keeps the index language generic only requiring decidability of equality of the index language providing a modular design. To illustrate the elegance and effectiveness of our language, we give programs for closure conversion and normalization by evaluation. Our three key technical contribution are: 1) We give a bidirectional type system for our core language which is centered around refinement substitutions instead of constraint solving. As a consequence, type checking is decidable and easy to trust, although constraint solving may be undecidable. 2) We give a big-step environment based operational semantics with environments which lends itself to efficient implementation. 3) We prove our language to be type safe and have mechanized our theoretical development in the proof assistant Coq using the fresh approach to binding.

关键词： Logical frameworks higher-order abstract syntax dependent types recursive types

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The Implicit Calculus A New Foundation for Generic programming 12

The Implicit Calculus A New Foundation for Generic Programmi...

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33rd acm sigplan conference on programming language design and implementation

作者： Oliveira, Bruno C. d. S. Schrijvers, Tom Choi, Wontae Lee, Wonchan Yi, Kwangkeun Seoul Natl Univ Seoul 151 South Korea Univ Ghent Ghent Belgium

ISBN: (纸本)9781450312059

Generic programming (GP) is an increasingly important trend in programming languages. Well-known GP mechanisms, such as type classes and the C++0x concepts proposal, usually combine two features: 1) a special type of interfaces;and 2) implicit instantiation of implementations of those interfaces. Scala implicits are a GP language mechanism, inspired by type classes, that break with the tradition of coupling implicit instantiation with a special type of interface. Instead, implicits provide only implicit instantiation, which is generalized to work for any types. This turns out to be quite powerful and useful to address many limitations that show up in other GP mechanisms. This paper synthesizes the key ideas of implicits formally in a minimal and general core calculus called the implicit calculus (lambda(double right arrow)), and it shows how to build source languages supporting implicit instantiation on top of it. A novelty of the calculus is its support for partial resolution and higher-order rules (a feature that has been proposed before, but was never formalized or implemented). Ultimately, the implicit calculus provides a formal model of implicits, which can be used by language designers to study and inform implementations of similar mechanisms in their own languages.

关键词： languages Implicit parameters type classes C plus plus concepts generic programming Haskell Scala

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Parcae: A System for Flexible Parallel Execution 12

Parcae: A System for Flexible Parallel Execution

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33rd acm sigplan conference on programming language design and implementation

作者： Raman, Arun Zaks, Ayal Lee, Jae W. August, David I. Intel Res Santa Clara CA USA Intel Corp Haifa Israel Sungkyunkwan Univ Suwon South Korea Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781450312059

Workload, platform, and available resources constitute a parallel program's execution environment. Most parallelization efforts statically target an anticipated range of environments, but performance generally degrades outside that range. Existing approaches address this problem with dynamic tuning but do not optimize a multiprogrammed system holistically. Further, they either require manual programming effort or are limited to array-based data-parallel programs. This paper presents Parcae, a generally applicable automatic system for platform-wide dynamic tuning. Parcae includes (i) the Nona compiler, which creates flexible parallel programs whose tasks can be efficiently reconfigured during execution;(ii) the Decima monitor, which measures resource availability and system performance to detect change in the environment;and (iii) the Morta executor, which cuts short the life of executing tasks, replacing them with other functionally equivalent tasks better suited to the current environment. Parallel programs made flexible by Parcae outperform original parallel implementations in many interesting scenarios.

关键词： design Performance automatic parallelization code generation compiler flexible multicore parallel performance portability run-time adaptivity tuning

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Logical Inference Techniques for Loop Parallelization 12

Logical Inference Techniques for Loop Parallelization

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33rd acm sigplan conference on programming language design and implementation

作者： Oancea, Cosmin E. Rauchwerger, Lawrence Univ Copenhagen HIPERFIT Dept Comp Sci DK-1168 Copenhagen Denmark Texas A&M Univ Parasol Lab College Stn TX 77843 USA

ISBN: (纸本)9781450312059

This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = empty set, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) double right arrow S = empty set). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F(S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECT-CLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers.

关键词： Performance design Algorithms auto-parallelization USR independence predicates

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Adaptive Input-aware Compilation for Graphics Engines 12

Adaptive Input-aware Compilation for Graphics Engines

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33rd acm sigplan conference on programming language design and implementation

作者： Samadi, Mehrzad Hormati, Amir Mehrara, Mojtaba Lee, Janghaeng Mahlke, Scott Univ Michigan Ann Arbor MI 48109 USA Microsoft Res Redmond WA USA NVIDIA Res Santa Clara CA USA

ISBN: (纸本)9781450312059

While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required to optimize applications is an obstacle to wider adoption of GPUs. In addition to the programmability challenges posed by GPU's complex memory hierarchy and parallelism model, a well-known application design problem is target portability across different GPUs. However, even for a single GPU target, changing a program's input characteristics can make an already-optimized implementation of a program perform poorly. In this work, we propose Adaptic, an adaptive input-aware compilation system to tackle this important, yet overlooked, input portability problem. Using this system, programmers develop their applications in a high-level streaming language and let Adaptic undertake the difficult task of input portable optimizations and code generation. Several input-aware optimizations are introduced to make efficient use of the memory hierarchy and customize thread composition. At runtime, a properly optimized version of the application is executed based on the actual program input. We perform a head-to-head comparison between the Adaptic generated and hand-optimized CUDA programs. The results show that Adaptic is capable of generating codes that can perform on par with their hand-optimized counterparts over certain input ranges and outperform them when the input falls out of the hand-optimized programs' "comfort zone". Furthermore, we show that input-aware results are sustainable across different GPU targets making it possible to write and optimize applications once and run them anywhere.

关键词： design languages Performance Streaming Compiler GPU Optimization Portability

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Chimera: Hybrid Program Analysis for Determinism 12

Chimera: Hybrid Program Analysis for Determinism

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33rd acm sigplan conference on programming language design and implementation

作者： Lee, Dongyoon Chen, Peter M. Flinn, Jason Narayanasamy, Satish Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781450312059

Chimera(1) uses a new hybrid program analysis to provide deterministic replay for commodity multiprocessor systems. Chimera leverages the insight that it is easy to provide deterministic multiprocessor replay for data-race-free programs (one can just record non-deterministic inputs and the order of synchronization operations), so if we can somehow transform an arbitrary program to be data-race-free, then we can provide deterministic replay cheaply for that program. To perform this transformation, Chimera uses a sound static data-race detector to find all potential data-races. It then instruments pairs of potentially racing instructions with a weak-lock, which provides sufficient guarantees to allow deterministic replay but does not guarantee mutual exclusion. Unsurprisingly, a large fraction of data-races found by the static tool are false data-races, and instrumenting them each of them with a weak-lock results in prohibitively high overhead. Chimera drastically reduces this cost from 53x to 1.39x by increasing the granularity of weak-locks without significantly compromising on parallelism. This is achieved by employing a combination of profiling and symbolic analysis techniques that target the sources of imprecision in the static data-race detector. We find that performance overhead for deterministic recording is 2.4% on average for Apache and desktop applications and about 86% for scientific applications.

关键词： design Performance Reliability Determinism Replay Data-race detection Static analysis Profiling Symbolic range analysis

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POPL: TLDI'12 - proceedings of the 8th acm sigplan Workshop on Types in language design and implementation

POPL: TLDI'12 - Proceedings of the 8th ACM SIGPLAN Workshop ...

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8th acm sigplan Workshop on Types in language design and implementation, TLDI'12, Co-located with POPL 2012

ISBN: (纸本)9781450311205

The proceedings contain 8 papers. The topics discussed include: towards concurrent type theory;exact type parameterization and this type support;types for relaxed memory models;towards a formal semantics for a structurally dynamic noncausal modelling language;semantics for graphical user interfaces;giving Haskell a promotion;static lock capabilities for deadlock freedom;type systems for dummies;and row-based effect types for database integration.

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Sound and Precise Analysis of Parallel Programs through Schedule Specialization 12

Sound and Precise Analysis of Parallel Programs through Sche...

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33rd acm sigplan conference on programming language design and implementation

作者： Wu, Jingyue Tang, Yang Hu, Gang Cui, Heming Yang, Junfeng Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781450312059

Parallel programs are known to be difficult to analyze. A key reason is that they typically have an enormous number of execution inter-leavings, or schedules. Static analysis over all schedules requires over-approximations, resulting in poor precision;dynamic analysis rarely covers more than a tiny fraction of all schedules. We propose an approach called schedule specialization to analyze a parallel program over only a small set of schedules for precision, and then enforce these schedules at runtime for soundness of the static analysis results. We build a schedule specialization framework for C/C++ multithreaded programs that use Pthreads. Our framework avoids the need to modify every analysis to be schedule-aware by specializing a program into a simpler program based on a schedule, so that the resultant program can be analyzed with stock analyses for improved precision. Moreover, our framework provides a precise schedule-aware def-use analysis on memory locations, enabling us to build three highly precise analyses: an alias analyzer, a data-race detector, and a path slicer. Evaluation on 17 programs, including 2 real-world programs and 15 popular benchmarks, shows that analyses using our framework reduced may-aliases by 61.9%, false race reports by 69%, and path slices by 48.7%;and detected 7 unknown bugs in well-checked programs.

关键词： Algorithms design Reliability Verification Specialization parallel programs multithreading control-flow analysis data-flow analysis constraint solving

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From Clarity to Efficiency for Distributed Algorithms 12

From Clarity to Efficiency for Distributed Algorithms

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acm International conference on Object Oriented programming Systems languages and Applications

作者： Liu, Yanhong A. Stoller, Scott D. Lin, Bo Gorbovitski, Michael SUNY Stony Brook Dept Comp Sci Stony Brook NY 11794 USA

ISBN: (纸本)9781450315616

This paper describes a very high-level language for clear description of distributed algorithms and optimizations necessary for generating efficient implementations. The language supports high-level control flows where complex synchronization conditions can be expressed using high-level queries, especially logic quantifications, over message history sequences. Unfortunately, the programs would be extremely inefficient, including consuming unbounded memory, if executed straightforwardly. We present new optimizations that automatically transform complex synchronization conditions into incremental updates of necessary auxiliary values as messages are sent and received. The core of the optimizations is the first general method for efficient implementation of logic quantifications. We have developed an operational semantics of the language, implemented a prototype of the compiler and the optimizations, and successfully used the language and implementation on a variety of important distributed algorithms.

关键词： Algorithms design languages Performance distributed algorithms incrementalization logic quantifications program optimization very high-level languages

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