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XMem: Type-safe, transparent, shared memory for cross-runtime communication and coordination

acm sigplan NOTICES 2008年第6期43卷 327-338页

作者： Wegiel, Michal Krintz, Chandra Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

Developers commonly build contemporary enterprise applications using type-safe, component-based platforms, such as J2EE, and architect them to comprise multiple tiers, such as a web container, application server, and database engine. Administrators increasingly execute each tier in its own managed runtime environment (MRE) to improve reliability and to manage system complexity through the fault containment and modularity offered by isolated MRE instances. Such isolation, however, necessitates expensive cross-tier communication based on protocols such as object serialization and remote procedure calls. Administrators commonly co-locate communicating MREs on a single host to reduce communication overhead and to better exploit increasing numbers of available processing cores. However, state-of-the-art MREs offer no support for more efficient communication between co-located MREs, while fast inter-process communication mechanisms, such as shared memory, are widely available as a standard operating system service on most modern platforms. To address this growing need, we present the design and implementation of XMem - type-safe, transparent, shared memory support for co-located MREs. XMem guarantees type-safety through coordinated, parallel, multi-process class loading and garbage collection. To avoid introducing any level of indirection, XMem manipulates virtual memory mapping. In addition, object sharing in XMem is fully transparent: shared objects are identical to local objects in terms of field access, synchronization, garbage collection, and method invocation, with the only difference being that shared-to-private pointers are disallowed. XMem facilitates easy integration and use by existing communication technologies and software systems, such as RMI, JNDI, JDBC, serialization/XML, and network sockets. We have implemented XMem in the open-source, production-quality HotSpot Java Virtual Machine. Our experimental evaluation, based on core communication technologies un

关键词： design experimentation languages management measurement performance interprocess communication managed runtimes shared memory transparent type-safe garbage collection synchronization class loading parallel

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TRANSIT: Specifying Protocols with Concolic Snippets 13

TRANSIT: Specifying Protocols with Concolic Snippets

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acm sigplan conference on programming language design and implementation

作者： Abhishek Udupa Sela Mador-Haim Arun Raghavan Milo M. K. Martin Jyotirmoy V. Deshmukh Rajeev Alur University of Pennsylvania Toyota Technical Center

ISBN: (纸本)9781450320146

With the maturing of technology for model checking and constraint solving, there is an emerging opportunity to develop programming tools that can transform the way systems are specified. In this paper, we propose a new way to program distributed protocols using concolic snippets. Concolic snippets are sample execution fragments that contain both concrete and symbolic values. The proposed approach allows the programmer to describe the desired system partially using the traditional model of communicating extended finite-state-machines (EFSM), along with high-level invariants and concrete execution fragments. Our synthesis engine completes an EFSM skeleton by inferring guards and updates from the given fragments which is then automatically analyzed using a model checker with respect to the desired invariants. The counterexamples produced by the model checker can then be used by the programmer to add new concrete execution fragments that describe the correct behavior in the specific scenario corresponding to the counterexample. We describe TRANSIT, a language and prototype implementation of the proposed specification methodology for distributed protocols. Experimental evaluations of TRANSIT to specify cache coherence protocols show that (1) the algorithm for expression inference from concolic snippets can synthesize expressions of size 15 involving typical operators over commonly occurring types, (2) for a classical directory-based protocol, TRANSIT automatically generates, in a few seconds, a complete implementation from a specification consisting of the EFSM structure and a few concrete examples for every transition, and (3) a published partial description of the SGI Origin cache coherence protocol maps directly to symbolic examples and leads to a complete implementation in a few iterations, with the programmer correcting counterexamples resulting from underspecified transitions by adding concrete examples in each iteration.

关键词： Program Synthesis Distributed Protocol Synthesis Cache Coherence Protocols programming by Example

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Tiling design patterns—a case study using the interpreter pattern 97

Tiling design patterns—a case study using the interpreter p...

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proceedings of the 12th acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： David H. Lorenz The Faculty of Computer Science Technion-Israel Institute of Technology Technion City Haifa 32000 Israel

ISBN: (纸本)9780897919081

This paper explains how patterns can be used to describe the implementation of other patterns. It is demonstrated how certain design patterns can describe their own design. This is a fundamental reflexive relationship in pattern relationships. The process of assembling patterns by other patterns is named pattern tiling. Tiling enables us to interweave simple understood concepts of patterns into their complex real-life implementation. Several pattern tilings for the Interpreter design pattern are illustrated.

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Scannerless NSLR(1) parsing of programming languages 89

Scannerless NSLR(1) parsing of programming languages

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proceedings of the acm sigplan 1989 conference on programming language design and implementation

作者： D. J. Salomon G. V. Cormack Department of Computer Science University of Waterloo Waterloo Ontario Canada

ISBN: (纸本)9780897913065

The disadvantages of traditional two-phase parsing (a scanner phase preprocessing input for a parser phase) are discussed. We present metalanguage enhancements for context-free grammars that allow the syntax of programming languages to be completely described in a single grammar. The enhancements consist of two new grammar rules, the exclusion rule, and the adjacency-restriction rule. We also present parser construction techniques for building parsers from these enhanced grammars, that eliminate the need for a scanner phase.

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Modeling usable & reusable transactors in SystemVerilog

Modeling usable & reusable transactors in SystemVerilog

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18th International conference on VLSI design: Power Aware design of VLSI Systems

作者： Bergeron, Janick Synopsys Synopsys's Verification Group

This paper describes how to properly use the object-oriented features of SystemVerilog to model transactions and transactors that execute them. designers, used to a procedural programming model, will learn how to approach a transactor modeling problem using the object-oriented approach. Software engineers, used to a traditional object-oriented programming model, will learn how to adapt their methods to the special requirements of constrained-random verification. This paper will present clear and concise guidelines that can be followed to create effective, easy-to-use and reusable transactor models. Summary: Transactors ? also known as bus-functional models ? have traditionally been modeled using a procedural interface (API). Commands were provided to use every feature available in the transactor. Several commands were often necessary to configure the transactor or to execute the simplest transaction. If the transactor did not provide a feature required by a particular device under test (DUT) or testcase, it had to be modified or rewritten. By using an object-oriented approach for configuration and interfacing, transactors can easily be used out-of-the-box. A few lines are all that is necessary to create valid random stimulus to a DUT or report observed response to a scoreboard. The use of callback methods eliminates the need for a complex and ever-evolving API. Instead of creating yet-another programming language, it leverages the power of SystemVerilog to extend the functionality of a transactor in ways the original author may not have conceived. Without modification, a ransactor can thus be used and reused effectively. Transactors can also be modeled in an extensible fashion. Extensible transactors allow users to define entirely new transactions and commands, should the ones provided by the original implementation prove insufficient. Usability and reusability of transactors does not happen by accident. With careful design and consistent use model, transactors can

关键词： Object oriented programming

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A single intermediate language that supports multiple implementations of exceptions 00

A single intermediate language that supports multiple implem...

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proceedings of the acm sigplan 2000 conference on programming language design and implementation

作者： Norman Ramsey Simon Peyton Jones Harvard University Microsoft Research Ltd

ISBN: (纸本)9781581131994

We present mechanisms that enable our compiler-target language, C--, to express four of the best known techniques for implementing exceptions, all within a single, uniform framework. We define the mechanisms precisely, using a formal operational semantics. We also show that exceptions need not require special treatment in the optimizer; by introducing extra dataflow edges, we make standard optimization techniques work even on programs that use exceptions. Our approach clarifies the design space of exception-handling techniques, and it allows a single optimizer to handle a variety of implementation techniques. Our ultimate goal is to allow a source-language compiler the freedom to choose its exception-handling policy, while encapsulating the architecture-dependent mechanisms and their optimization in an implementation of C--that can be used by compilers for many source languages.

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Sketching stencils

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acm sigplan NOTICES 2007年第6期42卷 167-178页

作者： Solar-Lezama, Armando Arnold, Gilad Tancau, Liviu Bodik, Rastislav Saraswat, Vijay Seshia, Sanjit IBM Corp TJ Watson Res Ctr Armonk NY 10504 USA Univ Calif Berkeley Berkeley CA 94720 USA

Performance of stencil computations can be significantly improved through smart implementations that improve memory locality, computation reuse, or parallelize the computation. Unfortunately, efficient implementations are hard to obtain because they often involve non-traditional transformations, which means that they cannot be produced by optimizing the reference stencil with a compiler. In fact, many stencils are produced by code generators that were tediously handcrafted. In this paper, we show how stencil implementations can be produced with sketching. Sketching is a software synthesis approach where the programmer develops a partial implementation a sketch-and a separate specification of the desired functionality given by a reference (unoptimized) stencil. The synthesizer then completes the sketch to behave like the specification, filling in code fragments that are difficult to develop manually. Existing sketching systems work only for small finite programs, i.e., programs that can be represented as small Boolean circuits. In this paper, we develop a sketching synthesizer that works for stencil computations, a large class of programs that, unlike circuits, have unbounded inputs and outputs, as well as an unbounded number of computations. The key contribution is a reduction algorithm that turns a stencil into a circuit, allowing us to synthesize stencils using an existing sketching synthesizer.

关键词： languages design performance sketching stencil SAT

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Component NextGen: A sound and expressive component framework for Java

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acm sigplan NOTICES 2007年第10期42卷 153-170页

作者： Sasitorn, James Cartwright, Robert Rice Univ Houston TX 77251 USA

Developing a general component system for a statically typed, object-oriented language is a challenging design problem for two reasons. First, mutually recursive references across components are common in object-oriented programs - an issue that has proven troublesome in the context of component systems for functional and procedural languages. Second, inheritance across component boundaries can cause accidental method overrides. Our recent research shows that a component framework can be constructed for a nominally typed object-oriented language supporting first-class(1) generic types simply by adding appropriate annotations, syntactic sugar, and component-level type-checking. The fundamental semantic building blocks for constructing, type-checking and manipulating components are provided by the underlying first-class generic type system. To demonstrate the simplicity and utility of this approach we have designed and implemented an extension of Java called Component NEXTGEN (CGEN). CGEN, which is based on the Sun Java 5.0 javac compiler, is backwards compatible with existing Java binary code and runs on current Java Virtual Machines. The primary contribution of this paper is a technical analysis of the subtle design issues involved in building a component framework for a nominally typed object-oriented language supporting first-class generics. In contrast to component systems for structurally typed languages, mutual recursion among components is accommodated in the type system and semantics without incorporating any special machinery. Our analysis includes a presentation of Core CGEN (CCG), a small, core language modeling the CGEN framework. It is based on Featherweight GJ and incorporates some ideas from MIXGEN. CCG adds the essential features to support components, but nothing more. Our discussion includes the type rules and semantics for CCG, as well as a proof of type safety.

关键词： design language first-class generics Java implementation custom class loader modules components signatures

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Incremental generation of parsers 89

Incremental generation of parsers

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proceedings of the acm sigplan 1989 conference on programming language design and implementation

作者： J. Heering P. Klint J. Rekers Department of Software Technology Centre for Mathematics and Computer Science P. 0. Box 4079 1009 AB Amsterdam The Netherlands Programming Research Group University of Amsterdam P. 0. Box 4 7 882 1009 DB Amsterdam The Netherlands

ISBN: (纸本)9780897913065

An LR-based parser generator for arbitrary context-free grammars is described, which generates parsers by need and processes grammar modifications by updating already existing parsers. We motivate the need for these techniques in the context of interactive language definition environments, present all required algorithms, and give measurements comparing their performance with that of conventional techniques.

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Methodology for hardware/software co-verification in C/C++ 00

Methodology for hardware/software co-verification in C/C++

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2000 Asia and South Pacific design Automation conference, ASP-DAC 2000

作者： Séméria, Luc Ghosh, Abhijit Computer System Lab. Stanford University United States Synopsys Inc. Mountain View CA United States

ISBN: (纸本)0780359747

In this paper we present our C/C++-based design environment for hardware/software co-verification. Our approach is to use C/C++ to describe both hardware and software throughout the design flow. Our methodology supports the efficient mapping of C/C++ functional descriptions directly into hardware and software. The advantages of a C/C++-based flow from the verification point of view are presented. The use of C/C++ to model all parts of the system provides great flexibility and enables faster simulation compared to existing methodologies. We show how co-verification can be done efficiently and effectively at the various levels of abstraction, how coverification can be used to drive co-design through performance estimation and give an example of implementation for the 8051 architecture. © 2000 IEEE.

关键词： C++ (programming language)

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