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Pluggable AOP: designing aspect mechanisms for third-party composition 05

Pluggable AOP: designing aspect mechanisms for third-party c...

proceedings of the 20th annual acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Sergei Kojarski David H. Lorenz University of Virginia Charlottesville VA

ISBN: (纸本)9781595930316

Studies of Aspect-Oriented programming (AOP) usually focus on a language in which a specific aspect extension is integrated with a base language. languages specified in this manner have a fixed, non-extensible AOP functionality. This paper argues the need for AOP to support the integration and use of multiple domain-specific aspect extensions together. We study the more general case of integrating a base language with a set of third-party aspect extensions for that language. We present a general mixin-based semantic framework for implementing dynamic aspect extensions in such a way that multiple, independently developed aspect mechanisms can be subject to third-party composition and work collaboratively. Principles governing the design of a collaborative aspect mechanism are aspectual effect exposure and implementation hiding.

关键词： aspectual effect aspect mechanism COOL domain-specific aspect language collaboration AOP reuse AspectJ AOP semantics third-party composition mixin aspect extension software components CBSE AOSD AspectWerkz

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Finding application errors and security flaws using PQL: a program query language

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acm sigplan NOTICES 2005年第10期40卷 365-383页

作者： Martin, M Livshits, B Lam, MS Stanford Univ Dept Comp Sci Stanford CA 94305 USA

A number of effective error detection tools have been built in recent years to check if a program conforrns to certain design rules. An important class of design rules deals with sequences of events associated with a set of related objects. This paper presents a language called PQL (Program Query language) that allows programmers to express such questions easily in an application-specific context. A query looks like a code excerpt corresponding to the shortest amount of code that would violate a design rule. Details of the target application's precise implementation are abstracted away. The programmer may also specify actions to perform when a match is found, such as recording relevant information or even correcting an erroneous execution on the fly. We have developed both static and dynamic techniques to find solutions to PQL queries. Our static analyzer finds all potential matches conservatively using a context-sensitive, flow-insensitive, inclusion-based pointer alias analysis. Static results are also useful in reducing the number of instrumentation points for dynamic analysis. Our dynamic analyzer instruments the source program to catch all violations precisely as the program runs and to optionally perform user-specified actions. We have implemented the techniques described in this paper and found 206 errors in 6 large real-world open-source Java applications containing a total of nearly 60,000 classes. These errors are important security flaws, resource leaks, and violations of consistency invariants. The combination of static and dynamic analysis proves effective at addressing a wide range of debugging and program comprehension queries. We have found that dynamic analysis is especially suitable for preventing errors such as security vulnerabilities at runtime.

关键词： languages security reliability program traces pattern matching web applications SQL injection resource leaks bug finding

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Toward Compositional Verification of Interruptible OS Kernels and Device Drivers

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acm sigplan NOTICES 2016年第6期51卷 431-447页

作者： Chen, Hao Wu, Xiongnan (Newman) Shao, Zhong Lockerman, Joshua Gu, Ronghui Univ Elect Sci & Technol China UESTC Chengdu Peoples R China Yale Univ New Haven CT 06520 USA

An operating system (OS) kernel forms the lowest level of any system software stack. The correctness of the OS kernel is the basis for the correctness of the entire system. Recent efforts have demonstrated the feasibility of building formally verified general-purpose kernels, but it is unclear how to extend their work to verify the functional correctness of device drivers, due to the non-local effects of interrupts. In this paper, we present a novel compositional framework for building certified interruptible OS kernels with device drivers. We provide a general device model that can be instantiated with various hardware devices, and a realistic formal model of interrupts, which can be used to reason about interruptible code. We have realized this framework in the Coq proof assistant. To demonstrate the effectiveness of our new approach, we have successfully extended an existing verified non-interruptible kernel with our framework and turned it into an interruptible kernel with verified device drivers. To the best of our knowledge, this is the first verified interruptible operating system with device drivers.

关键词： Verification Reliability Security languages design Program Verification Certified OS Kernels Interrupts Device Drivers Abstraction Layer Modularity

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The design and implementation of a certifying compiler 98

The design and implementation of a certifying compiler

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proceedings of the acm sigplan 1998 conference on programming language design and implementation

作者： George C. Necula Peter Lee School of Computer Science Carnegie Mellon University Pittsburgh Pennsylvania

ISBN: (纸本)9780897919876

This paper presents the design and implementation of a compiler that translates programs written in a type-safe subset of the C programming language into highly optimized DEC Alpha assembly language programs, and a certifier that automatically checks the type safety and memory safety of any assembly language program produced by the compiler. The result of the certifier is either a formal proof of type safety or a counterexample pointing to a potential violation of the type system by the target program. The ensemble of the compiler and the certifier is called a certifying *** advantages of certifying compilation over previous approaches can be claimed. The notion of a certifying compiler is significantly easier to employ than a formal compiler verification, in part because it is generally easier to verify the correctness of the result of a computation than to prove the correctness of the computation itself. Also, the approach can be applied even to highly optimizing compilers, as demonstrated by the fact that our compiler generates target code, for a range of realistic C programs, which is competitive with both the cc and gcc compilers with all optimizations enabled. The certifier also drastically improves the effectiveness of compiler testing because, for each test case, it statically signals compilation errors that might otherwise require many executions to detect. Finally, this approach is a practical way to produce the safety proofs for a Proof-Carrying Code system, and thus may be useful in a system for safe mobile code.

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EXOCHI: Architecture and programming environment for a heterogeneous multi-core multithreaded system

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acm sigplan NOTICES 2007年第6期42卷 156-166页

作者： Wang, Perry H. Collins, Jamison D. Chinya, Gautham N. Hong Jiang Xinmin Tian Girkar, Milind Yang, Nick Y. Lueh, Guei-Yuan Wang, Hong Intel Corp Microprocessor Technol Labs Microarchitecture Res Lab Santa Clara CA 95051 USA Intel Corp Chipset Grp Santa Clara CA 95051 USA Intel Corp Software Solut Corp Intel Compiler Lab Santa Clara CA 95051 USA

Future mainstream microprocessors will likely integrate specialized accelerators, such as GPUs, onto a single die to achieve better performance and power efficiency. However, it remains a keen challenge to program such a heterogeneous multi-core platform, since these specialized accelerators feature ISAs and functionality that are significantly different from the general purpose CPU cores. In this paper, we present EXOCHI: (1) Exoskeleton Sequencer (EXO), an architecture to represent heterogeneous accelerators as ISA-based MIMD architecture resources, and a shared virtual memory heterogeneous multithreaded program execution model that tightly couples specialized accelerator cores with general purpose CPU cores, and (2) C for Heterogeneous Integration (CHI), an integrated C/C++ programming environment that supports accelerator-specific inline assembly and domain-specific languages. The CHI compiler extends the OpenMP pragma for heterogeneous multithreading programming, and produces a single fat binary with code sections corresponding to different instruction sets. The runtime can judiciously spread parallel computation across the heterogeneous cores to optimize performance and power. We have prototyped the EXO architecture on a physical heterogeneous platform consisting of an Intel (R) Core (TM) 2 Duo processor and an 8-core 32-thread Intel (R) Graphics Media Accelerator X3000. In addition, we have implemented the CHI integrated programming environment with the Intel (R) C++ Compiler, runtime toolset, and debugger. On the EXO prototype system, we have enhanced a suite of production-quality media kernels for video and image processing to utilize the accelerator through the CHI programming interface, achieving significant speedup (1.41X to 10.97X) over execution on the IA32 CPU alone.

关键词： performance design languages heterogeneous multi-cores GPU OpenMP

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CLAP: Recording Local Executions to Reproduce Concurrency Failures 13

CLAP: Recording Local Executions to Reproduce Concurrency Fa...

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acm sigplan conference on programming language design and implementation

作者： Jeff Huang Charles Zhang Julian Dolby Hong Kong University of Science and Technology IBM Thomas J. Watson Research Center

ISBN: (纸本)9781450320146

We present CLAP, a new technique to reproduce concurrency bugs. CLAP has two key steps. First, it logs thread local execution paths at runtime. Second, offline, it computes memory dependencies that accord with the logged execution and are able to reproduce the observed bug. The second step works by combining constraints from the thread paths and constraints based on a memory model, and computing an execution with a constraint solver. CLAP has four major advantages. First, logging purely local execution of each thread is substantially cheaper than logging memory interactions, which enables CLAP to be efficient compared to previous approaches. Second, our logging does not require any synchronization and hence with no added memory barriers or fences; this minimizes perturbation and missed bugs due to extra synchronizations foreclosing certain racy behaviors. Third, since it uses no synchronization, we extend CLAP to work on a range of relaxed memory models, such as TSO and PSO, in addition to sequential consistency. Fourth, CLAP can compute a much simpler execution than the original one, that reveals the bug with minimal thread context switches. To mitigate the scalability issues, we also present an approach to parallelize constraint solving, which theoretically scales our technique to programs with arbitrary execution length. Experimental results on a variety of multithreaded benchmarks and real world concurrent applications validate these advantages by showing that our technique is effective in reproducing concurrency bugs even under relaxed memory models; furthermore, it is significantly more efficient than a state-of-the-art technique that records shared memory dependencies, reducing execution time overhead by 45% and log size by 88% on average.

关键词： Concurrency Bug Reproduction Local Execution Constraint Solving Algorithms design Performance Theory

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CAPSULE: language and system support for efficient state sharing in distributed stream processing systems 12

CAPSULE: Language and system support for efficient state sha...

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6th acm International conference on Distributed Event-Based Systems, DEBS'12

作者： Losa, Giuliano Kumar, Vibhore Andrade, Henrique Gedik, Buǧra Hirzel, Martin Soulé, Robert Wu, Kun-Lung Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland Thomas J. Watson Research Center IBM Research 19 Skyline Drive Hawthorne NY 10532 United States Department of Computer Engineering Bilkent University Bilkent Ankara 06800 Turkey

ISBN: (纸本)9781450313155

Data stream processing applications are often expressed as data flow graphs, composed of operators connected via streams. This structured representation provides a simple yet powerful paradigm for building large-scale, distributed, high-performance applications. However, there are many tasks that require sharing data across operators, and across operators and the runtime using a less structured mechanism than point-to-point data flows. Examples include updating control variables, sending notifications, collecting metrics, building collective models, etc. In this paper we describe CAPSULE, which fills this gap. CAPSULE is a code generation and runtime framework that offers an easy to use and highly flexible framework for developers to realize shared variables (CAPSULE term for shared state) by specifying a data structure (at the programming-language level), and a few associated configuration parameters that qualify the expected usage scenario. Besides the easy of use and flexibility, CAPSULE offers the following important benefits: (1) Custom Code Generation - CAPSULE makes use of user-specified configuration parameters and information from the runtime to generate shared variable servers that are tailored for the specific usage scenario, (2) Composability - CAPSULE supports deployment time composition of the shared variable servers to achieve desired levels of scalability, performance and fault-tolerance, and (3) Extensibility - CAPSULE provides simple interfaces for extending the CAPSULE framework with more protocols, transports, caching mechanisms, etc. We describe the motivation for CAPSULE and its design, report on its implementation status, and then present experimental results. Copyright © 2012 acm.

关键词： Fault tolerance

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Behind Every Great Deep Learning Framework Is an Even Greater programming languages Concept (Keynote) 2018

Behind Every Great Deep Learning Framework Is an Even Greate...

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26th acm Joint Meeting on European Software Engineering conference (ESEC) / Symposium on the Foundations of Software Engineering (FSE)

作者： Meijer, Erik Delft Univ Technol Software Engn Res Grp Cloud Programming Delft Netherlands Facebook Infra Struct Org Menlo Pk CA 94025 USA

ISBN: (纸本)9781450355735

In many areas, such as image recognition, natural language processing, search, recommendation, autonomous cars, systems software and infrastructure, and even Software Engineering tools themselves, Software 2.0 (= programming using learned models) is quickly swallowing Software 1.0 (= programming using handcrafted algorithms). Where the Software 1.0 Engineer formally specifies their problem, carefully designs algorithms, composes systems out of subsystems or decomposes complex systems into smaller components, the Software 2.0 Engineer amasses training data and simply feeds it into an ML algorithm that will synthesize an approximation of the function whose partial extensional definition is that training data. Instead of code as the artifact of interest, in Software 2.0 it is all about the data where compilation of source code is replaced by training models with data. This new style of programming has far-reaching consequences for traditional software engineering practices. Everything we have learned about life cycle models, project planning and estimation, requirements analysis, program design, construction, debugging, testing, maintenance and implementation, ... runs the danger of becoming obsolete. One way to try to prepare for the new realities of software engineering is not to zero in on the differences between Software 1.0 and Software 2.0 but instead focus on their similarities. If you carefully look at what a neural net actually represents, you realize that in essence it is a pure function, from multi-dimensional arrays of floating point numbers to multi-dimensional arrays of floating point numbers (tensors). What is special about these functions is that they are differentiable (yes, exactly as you remember from middle school calculus), which allows them to be trained using back propagation. The programming language community has also discovered that there is a deep connection between back propagation and continuations. Moreover, when you look closely at how So

关键词： Machine Learning programming languages Functional programming Automatic Differentiation Differentiable programming Deep Learning Continuation Passing Style

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Riposte: A Trace-Driven Compiler and Parallel VM for Vector Code in R 12

Riposte: A Trace-Driven Compiler and Parallel VM for Vector ...

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21st International conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Talbot, Justin DeVito, Zachary Hanrahan, Pat Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450311823

There is a growing utilization gap between modern hardware and modern programming languages for data analysis. Due to power and other constraints, recent processor design has sought improved performance through increased SIMD and multi-core parallelism. At the same time, high-level, dynamically typed languages for data analysis have become popular. These languages emphasize ease of use and high productivity, but have, in general, low performance and limited support for exploiting hardware parallelism. In this paper, we describe Riposte, a new runtime for the R language, which bridges this gap. Riposte uses tracing, a technique commonly used to accelerate scalar code, to dynamically discover and extract sequences of vector operations from arbitrary R code. Once extracted, we can fuse traces to eliminate unnecessary memory traffic, compile them to use hardware SIMD units, and schedule them to run across multiple cores, allowing us to fully utilize the available parallelism on modern shared-memory machines. Our evaluation shows that Riposte can run vector R code near the speed of hand-optimized C, 5-50x faster than the open source implementation of R, and can also linearly scale to 32 cores for some tasks. Across 12 different workloads we achieve an overall average speed-up of over 150x without explicit programmer parallelization.

关键词： R language just-in-time compilation tracing data parallel

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Taming the IXP network processor 03

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proceedings of the acm sigplan 2003 conference on programming language design and implementation

作者： Lal George Matthias Blume Network Speed Technologies Inc Toyota Technological Institute at Chicago

ISBN: (纸本)9781581136623

We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal bank assignment, and spills. The compiler's optimizer employs CPS as its intermediate representation; some of the invariants that this IR guarantees are essential for the formulation of a practical ILP *** and George used a similar ILP-based technique for the IA32 to decide which variables reside in registers but deferred the actual assignment of colors to a later phase. We demonstrate how to carry over their idea to an architecture with many more banks, register aggregates, variables with multiple simultaneous register assignments, and, very importantly, one where bank- and register-assignment cannot be done in isolation from each other. Our approach performs well in practise---without causing an explosion in size or solve time of the generated integer linear programs.

关键词： bank assignment network processors integer linear programming programming languages code generation Intel IXA register allocation

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