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检索条件"任意字段=Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation"

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design automation for Ada development under DOD-STD-2167 (and beyond) 87

Design automation for Ada development under DOD-STD-2167 (an...

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proceedings of the 1987 annual acm SIGAda international conference on Ada

作者： Brett Bachman

ISBN: (纸本)9780897912433

The combination of Ada® used as a programming language and as a program design language (PDL) can effectively help automate the enforcement of design methods and the creation of design documentation. This paper discusses how design automation can be applied successfully to the development of complex Ada systems under DOD-STD-2167. In particular, the use of an Ada-based PDL as the basis for capturing design decisions is examined. The paper also explores the implications of such an approach in the context of integrated tool support, namely, the ability to produce documents automatically, to enforce project-specific design rules, to provide interactive traversing between design and implementation, and to facilitate traceability.

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Incrementalization across object abstraction 05

Incrementalization across object abstraction

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proceedings of the 20th annual acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Yanhong A. Liu Scott D. Stoller Michael Gorbovitski Tom Rothamel Yanni Ellen Liu State University of New York at Stony Brook Stony Brook NY University of Manitoba Winnipeg MB Canada

ISBN: (纸本)9781595930316

Object abstraction supports the separation of what operations are provided by systems and components from how the operations are implemented, and is essential in enabling the construction of complex systems from components. Unfortunately, clear and modular implementations have poor performance when expensive query operations are repeated, while efficient implementations that incrementally maintain these query results are much more difficult to develop and to understand, because the code blows up significantly, and is no longer clear or *** paper describes a powerful and systematic method that first allows the "what" of each component to be specified in a clear and modular fashion and implemented straightforwardly in an object-oriented language; then analyzes the queries and updates, across object abstraction, in the straightforward implementation; and finally derives the sophisticated and efficient "how" of each component by incrementally maintaining the results of repeated expensive queries with respect to updates to their parameters. Our implementation and experimental results for example applications in query optimization, role-based access control, etc. demonstrate the effectiveness and benefit of the method.

关键词： program analysis design invariants program optimization incrementalization object-oriented abstraction program transformation

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The design and performance of a real-time CORBA event service 97

The design and performance of a real-time CORBA event servic...

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proceedings of the 12th acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Timothy H. Harrison David L. Levine Douglas C. Schmidt Department of Computer Science Washington University St. Louis MO

ISBN: (纸本)9780897919081

The CORBA Event Service provides a flexible model for asynchronous communication among objects. However, the standard CORBA Event Service specification lacks important features required by real-time applications. For instance, operational flight programs for fighter aircraft have complex real-time processing requirements. This paper describes the design and performance of an object-oriented, real-time implementation of the GORBA Event Service that is designed to meet these *** paper makes three contributions to the design and performance measurement of object-oriented real-time systems. First, it illustrates how to extend the CORBA Event Service so that it is suitable for real-time systems. These extensions support periodic rate-based event processing and efficient event filtering and correlation. Second, it describes how to develop object-oriented event dispatching and scheduling mechanisms that can provide real-time guarantees. Finally, the paper presents benchmarks that demonstrate the performance tradeoffs of alternative concurrent dispatching mechanisms for real-time Event Services.

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Lightweight object-oriented shared variables for distributed applications on the Internet 98

Lightweight object-oriented shared variables for distributed...

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proceedings of the 13th acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Jacob Harris Vivek Sarkar Massachusetts Institute of Technology IBM T. J. Watson Research Center

ISBN: (纸本)9781581130058

This paper describes a lightweight yet powerful approach for writing distributed applications using shared variables. Our approach, called SHAREHOLDER, is inspired by the flexible and intuitive model of information access common to the World Wide Web. The distributed applications targeted by our approach all share a weak consistency model and loose transaction semantics, similar to a user's model of accessing email, bulletin boards, chat rooms, etc. on the Internet. The SHAREHOLDER infrastructure has several advantages. Its highly object-oriented view of shared variables simplifies their initialization and configuration. A shared variable's distribution mechanism is specified through an associated configuration object, and the programmer does not need to write any extra code to implement the sharing mechanism. These configuration objects can be initialized at run-time, allowing tremendous flexibility in dynamic control of distribution of shared variables. Finally, the programmer can treat shared variables and local variables interchangeably, thus simplifying conversion of a serial application into a distributed application.

关键词： language design and implementation persistence world wide web distributed and parallel systems

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Featherweight Java: a minimal core calculus for Java and GJ 99

Featherweight Java: a minimal core calculus for Java and GJ

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proceedings of the 14th acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Atshushi Igarashi Benjamin Pierce Philip Wadler Dept. of Comp. & Info. Sci. University of Pennsylvania Bell Laboratories Lucent Technologies

ISBN: (纸本)9781581132380

Several recent studies have introduced lightweight versions of Java: reduced languages in which complex features like threads and reflection are dropped to enable rigorous arguments about key properties such as type safety. We carry this process a step further, omitting almost all features of the full language (including interfaces and even assignment) to obtain a small calculus, Featherweight Java, for which rigorous proofs are not only possible but *** Java bears a similar relation to full Java as the lambda-calculus does to languages such as ML and Haskell. It offers a similar computational “feel,” providing classes, methods, fields, inheritance, and dynamic typecasts, with a semantics closely following Java's. A proof of type safety for Featherweight Java thus illustrates many of the interesting features of a safety proof for the full language, while remaining pleasingly compact. The syntax, type rules, and operational semantics of Featherweight Java fit on one page, making it easier to understand the consequences of extensions and *** an illustration of its utility in this regard, we extend Featherweight Java with generic classes in the style of GJ (Bracha, Odersky, Stoutamire, and Wadler) and sketch a proof of type safety. The extended system formalizes for the first time some of the key features of GJ.

关键词： language design implementation theoretical foundations

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A compiler approach to fast hardware design space exploration in FPGA-based systems 02

A compiler approach to fast hardware design space exploratio...

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proceedings of the acm sigplan 2002 conference on programming language design and implementation

作者： Byoungro So Mary W. Hall Pedro C. Diniz University of Southern California Marina del Rey California

ISBN: (纸本)9781581134636

The current practice of mapping computations to custom hardware implementations requires programmers to assume the role of hardware designers. In tuning the performance of their hardware implementation, designers manually apply loop transformations such as loop unrolling. designers manually apply loop transformations. For example, loop unrolling is used to expose instruction-level parallelism at the expense of more hardware resources for concurrent operator evaluation. Because unrolling also increases the amount of data a computation requires, too much unrolling can lead to a memory bound implementation where resources are idle. To negotiate inherent hardware space-time trade-offs, designers must engage in an iterative refinement cycle, at each step manually applying transformations and evaluating their impact. This process is not only error-prone and tedious but also prohibitively expensive given the large search spaces and with long synthesis times. This paper describes an automated approach to hardware design space exploration, through a collaboration between parallelizing compiler technology and high-level synthesis tools. We present a compiler algorithm that automatically explores the large design spaces resulting from the application of several program transformations commonly used in application-specific hardware designs. Our approach uses synthesis estimation techniques to quantitatively evaluate alternate designs for a loop nest computation. We have implemented this design space exploration algorithm in the context of a compilation and synthesis system called DEFACTO, and present results of this implementation on five multimedia kernels. Our algorithm derives an implementation that closely matches the performance of the fastest design in the design space, and among implementations with comparable performance, selects the smallest design. We search on average only 0.3% of the design space. This technology thus significantly raises the level of abstraction fo

关键词： design space exploration data dependence analysis reuse analysis loop transformations

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Halide: a language and compiler for optimizing parallelism, locality, and recomputation in image processing pipelines 13

Halide: a language and compiler for optimizing parallelism, ...

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proceedings of the 34th acm sigplan conference on programming language design and implementation

作者： Jonathan Ragan-Kelley Connelly Barnes Andrew Adams Sylvain Paris Frédo Durand Saman Amarasinghe Massachusetts Institute of Technology Cambridge MA USA Adobe Cambridge MA USA

ISBN: (纸本)9781450320146

Image processing pipelines combine the challenges of stencil computations and stream programs. They are composed of large graphs of different stencil stages, as well as complex reductions, and stages with global or data-dependent access patterns. Because of their complex structure, the performance difference between a naive implementation of a pipeline and an optimized one is often an order of magnitude. Efficient implementations require optimization of both parallelism and locality, but due to the nature of stencils, there is a fundamental tension between parallelism, locality, and introducing redundant recomputation of shared *** present a systematic model of the tradeoff space fundamental to stencil pipelines, a schedule representation which describes concrete points in this space for each stage in an image processing pipeline, and an optimizing compiler for the Halide image processing language that synthesizes high performance implementations from a Halide algorithm and a schedule. Combining this compiler with stochastic search over the space of schedules enables terse, composable programs to achieve state-of-the-art performance on a wide range of real image processing pipelines, and across different hardware architectures, including multicores with SIMD, and heterogeneous CPU+GPU execution. From simple Halide programs written in a few hours, we demonstrate performance up to 5x faster than hand-tuned C, intrinsics, and CUDA implementations optimized by experts over weeks or months, for image processing applications beyond the reach of past automatic compilers.

关键词： autotuning parallelism locality compiler vectorization gpu redundant computation optimization domain specific language image processing

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The development of a large scale mathematical programming system 68

The development of a large scale mathematical programming sy...

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proceedings of the 1968 23rd acm national conference

作者： Jacques De Buchet

ISBN: (纸本)9781450374866

The general purpose mathematical programming systems have greatly changed in the last few years and the aim of such codes is no longer to give access to an efficient algorithm but to integrate the solution of linear programming problems into a loop including the generation of the problem, its solution, its post optimal analysis and the edition of an output report of the results. The link between all these operations is done through a so-called control language *** these aspects are more or less the same from one code to another but we think that new approaches should be brought into their design, organization, and implementation. The development cost of such programs being very high, usually in the order of 15 to 30 man years, it is necessary to provide facilities in order to:- offer suitable users and programming languages;- have a modular design;- handle memory allocation in a semi-optimal way;- make modifications and extensions easier; and- facilitate day to day programmers tasks.I shall present, in the following pages, the objectives that we had in mind when we began to implement these facilities within the large scale mathematical programming system OPHELIE 2 which we developed for the CDC 6600.

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Small: A programming language for state machine design

Small: A programming language for state machine design

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Canadian conference on Electrical and Computer Engineering (CCECE)

作者： T.S. Norvell Faculty of Engineering Memorial University of Newfoundland Saint John's NEW Canada

A small and simple language for sequential design is introduced. Synchronous state-machine design is often expressed using graphical notations such as Algorithmic State Machine (ASM) charts and state transition diagrams. An alternative is to use common hardware description languages such as VHDL or Verilog. For both teaching and design purposes, neither approach is satisfactory. ASM charts and similar notations invite unstructured designs and allow parallelism only at the outermost level. Educational implementations appear not to exist. VHDL and Verilog are geared toward asynchronous behaviour - in expressing synchronous designs the clock signals must be made explicit. Also they are large, complex languages with complex semantic foundations. SMALL (State Machine Algol-Like language) is a small and simple imperative programming language, designed specifically for hardware implementation. It bears roughly the same relationship to ASM charts as Algol-like software languages bear to flowcharts.

关键词： Computer languages Clocks Hardware design languages design engineering Noise measurement Algorithm design and analysis Education Signal design Flowcharts

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Experience with a language for writing coherence protocols

Experience with a language for writing coherence protocols

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1997 conference on Domain-Specific languages, DSL 1997

作者： Chandra, Satish Dahlin, Michael Richards, Bradley Wang, Randolph Y. Anderson, Thomas E. Larus, James R. University of Wisconsin Madison United States University of Texas Austin United States Vassar College University of California Berkeley United States

In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distributed computing systems make local replicas of shared data to improve scalability and performance. In both distributed shared memory systems and distributed file systems, a coherence protocol maintains agreement among the replicated copies as the underlying data are modified by programs running on the system. Cache coherence protocols are notoriously difficult to implement, debug, and maintain. Unfortunately, protocols are not off-the-shelf items, as their details depend on the requirements of the system under consideration. This paper presents case studies detailing the successes and shortcomings of using Teapot for writing coherence protocols in two systems. The first system, loosely coherent memory (LCM) [16], implements a particular type of distributed shared memory suitable for data-parallel programming. The second system, the xFS distributed Gle system [9], implements a high-performance, serverless file system. Our overall experience with Teapot has been very positive. In particular, Teapot's language features resulted in considerable simplifications in the protocol source code for both systems. Furthermore, Teapot's close coupling between implementation and formal verification helped to achieve much higher confidence in our protocol implementations than previously possible and reduced the time to build the protocols. By using Teapot to solve real problems in complex systems, we also discovered several shortcomings of the Teapot design. Most noticeably, we found Teapot lacking in support for multithreaded environments, for expressing actions that transcend several cache blocks, and for handling blocking system calls. We believe that domain-specific languages are valuable tools for writing cache coherence protocols. © Domain-Specific languages, DSL *** right reserved.

关键词： Memory architecture

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