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Component NextGen: A sound and expressive component framework for Java

acm sigplan NOTICES 2007年第10期42卷 153-170页

作者： Sasitorn, James Cartwright, Robert Rice Univ Houston TX 77251 USA

Developing a general component system for a statically typed, object-oriented language is a challenging design problem for two reasons. First, mutually recursive references across components are common in object-oriented programs - an issue that has proven troublesome in the context of component systems for functional and procedural languages. Second, inheritance across component boundaries can cause accidental method overrides. Our recent research shows that a component framework can be constructed for a nominally typed object-oriented language supporting first-class(1) generic types simply by adding appropriate annotations, syntactic sugar, and component-level type-checking. The fundamental semantic building blocks for constructing, type-checking and manipulating components are provided by the underlying first-class generic type system. To demonstrate the simplicity and utility of this approach we have designed and implemented an extension of Java called Component NEXTGEN (CGEN). CGEN, which is based on the Sun Java 5.0 javac compiler, is backwards compatible with existing Java binary code and runs on current Java Virtual Machines. The primary contribution of this paper is a technical analysis of the subtle design issues involved in building a component framework for a nominally typed object-oriented language supporting first-class generics. In contrast to component systems for structurally typed languages, mutual recursion among components is accommodated in the type system and semantics without incorporating any special machinery. Our analysis includes a presentation of Core CGEN (CCG), a small, core language modeling the CGEN framework. It is based on Featherweight GJ and incorporates some ideas from MIXGEN. CCG adds the essential features to support components, but nothing more. Our discussion includes the type rules and semantics for CCG, as well as a proof of type safety.

关键词： design language first-class generics Java implementation custom class loader modules components signatures

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The design of a parallel graphics interface 98

The design of a parallel graphics interface

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25th Annual conference on Computer Graphics and Interactive Techniques, SIGGRAPH 1998

作者： Igehy, Homan Stoll, Gordon Hanrahan, Pat Computer Science Department Stanford University United States

ISBN: (纸本)0897919998

It has become increasingly difficult to drive a modern high-performance graphics accelerator at full speed with a serial immediate-mode graphics interface. To resolve this problem, retained-mode constructs have been integrated into graphics interfaces. While retained-mode constructs provide a good solution in many cases, at times they provide an undesirable interface model for the application programmer, and in some cases they do not solve the performance problem. In order to resolve some of these cases, we present a parallel graphics interface that may be used in conjunction with the existing API as a new paradigm for high-performance graphics applications. The parallel API extends existing ideas found in OpenGL and X11 that allow multiple graphics contexts to simultaneously draw into the same image. Through the introduction of synchronization primitives, the parallel API allows parallel traversal of an explicitly ordered scene. We give code examples which demonstrate how the API can be used to expose parallelism while retaining many of the desirable features of serial immediate-mode programming. The viability of the API is demonstrated by the performance of our implementation which achieves scalable performance on a 24 processor system.

关键词： Application programming interfaces (API)

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Parallel Architectures and Compilation Techniques - conference proceedings, PACT

Parallel Architectures and Compilation Techniques - Conferen...

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1998 International conference on Parallel Architectures and Compilation Techniques, PACT 1998

ISBN: (纸本)0818685913

The proceedings contain 50 papers. The topics discussed include: integrating loop and data transformations for global optimization;optical versus electronic bus for address-transactions in future SMP architectures;Origin 2000 design enhancements for communication intensive applications;design study of shared memory in VLIW video signal processors;exploiting fine- and coarse-grain parallelism in embedded programs;eliminating bottlenecks on parallel systems using adaptive objects;Athapascan-1: on-line building data flow graph in a parallel language;code generation in the polytope model;capturing the effects of code improving transformations;fast, accurate and flexible data locality analysis;superscalar execution with direct data forwarding;a fast interrupt handling scheme for VLIW processors;efficacy and performance impact of value prediction;a fast algorithm for scheduling time-constrained instructions on processors with ILP;exploiting method-level parallelism in single-threaded java programs;improving static branch prediction in a compiler;static methods in hybrid branch prediction;Madeleine: an efficient and portable communication interface for RPC-based multithreaded environments;breaking the barriers: two models for MPI programming;performance of message-passing systems using a zero-copy communication protocol;dynamic hammock predication for non-predicated instruction set architectures;and an direct-execution framework for fast and accurate simulation of superscalar processors.

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Customization: optimizing compiler technology for SELF, a dynamically-typed object-oriented programming language 89

Customization: optimizing compiler technology for SELF, a dy...

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proceedings of the acm sigplan 1989 conference on programming language design and implementation

作者： C. Chambers D. Ungar Stanford University

ISBN: (纸本)9780897913065

Dynamically-typed object-oriented languages please programmers, but their lack of static type information penalizes performance. Our new implementation techniques extract static type information from declaration-free programs. Our system compiles several copies of a given procedure, each customized for one receiver type, so that the type of the receiver is bound at compile time. The compiler predicts types that are statically unknown but likely, and inserts run-time type tests to verify its predictions. It splits calls, compiling a copy on each control path, optimized to the specific types on that path. Coupling these new techniques with compile-time message lookup, aggressive procedure inlining, and traditional optimizations has doubled the performance of dynamically-typed object-oriented languages.

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Mdspan in C++: A Case Study in the Integration of Performance Portable Features into International language Standards

Mdspan in C++: A Case Study in the Integration of Performanc...

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2019 IEEE/acm International Workshop on Performance, Portability and Productivity in HPC, P3HPC 2019

作者： Hollman, David Lelbach, Bryce Edwards, H. Carter Hoemmen, Mark Sunderland, Daniel Trott, Christian R. Scalable Modeling and Analysis Sandia National Laboratories LivermoreCA United States NVIDIA Corp. Santa ClaraCA United States Engineering Sciences Sandia National Laboratories AlbuquerqueNM United States Center for Computing Research Sandia National Laboratories AlbuquerqueNM United States

ISBN: (纸本)9781728160030

Multi-dimensional arrays are ubiquitous in high-performance computing (HPC), but their absence from the C++ language standard is a long-standing and well-known limitation of their use for HPC. This paper describes the design and implementation of mdspan, a proposed C++ standard multidimensional array view (planned for inclusion in C++23). The proposal is largely inspired by work done in the Kokkos project - a C++ performance-portable programming model de- ployed by numerous HPC institutions to prepare their code base for exascale-class supercomputing systems. This paper describes the final design of mdspan af- ter a five-year process to achieve consensus in the C++ community. In particular, we will lay out how the design addresses some of the core challenges of performance-portable programming, and how its cus- tomization points allow a seamless extension into areas not currently addressed by the C++ Standard but which are of critical importance in the heterogeneous computing world of today's systems. Finally, we have provided a production-quality implementation of the proposal in its current form. This work includes several benchmarks of this implementation aimed at demon- strating the zero-overhead nature of the modern design. © 2019 IEEE.

关键词： C++ (programming language)

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Merge: A programming model for heterogeneous multi-core systems

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acm sigplan NOTICES 2008年第3期43卷 287-296页

作者： Linderman, Michael D. Collins, Jamison D. Wang, Hong Meng, Teresa H. Stanford Univ Dept Elect Engn Stanford CA 94305 USA Intel Corp Microarchitecture Res Lab Santa Cruz CA USA

In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to parallel programming on heterogeneous platforms with a rigorous, library-based methodology that can automatically distribute computation across heterogeneous cores to achieve increased energy and performance efficiency. The Merge framework provides (1) a predicate dispatch-based library system for managing and invoking function variants for multiple architectures;(2) a high-level, library-oriented parallel language based on map-reduce;and (3) a compiler and runtime which implement the map-reduce language pattern by dynamically selecting the best available function implementations for a given input and machine configuration. Using a generic sequencer architecture interface for heterogeneous accelerators, the Merge framework can integrate function variants for specialized accelerators, offering the potential for to-the-metal performance for a wide range of heterogeneous architectures, all transparent to the user. The Merge framework has been prototyped on a heterogeneous platform consisting of an Intel Core 2 Duo CPU and an 8-core 32-thread Intel Graphics and Media Accelerator X3000, and a homogeneous 32-way Unisys SNIP system with Intel Xeon processors. We implemented a set of benchmarks using the Merge framework and enhanced the library with X3000 specific implementations, achieving speedups of 3.6x - 8.5x using the X3000 and 5.2x - 22x using the 32-way system relative to the straight C reference implementation on a single IA32 core.

关键词： performance design languages heterogeneous multi-core GPGPU predicate dispatch

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Towards an engineering approach to software design 2

Towards an engineering approach to software design

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2nd International conference on Software Engineering, ICSE 1976

作者： White, John R. Booth, Taylor L. Department of Electrical Engineering and Computer Science University of Connecticut StorrsCT United States

The software design process is discussed from an engineering point of view. Initially, a distinction is made between software design and program design. Software design is then described in terms of evolving a system architecture independently of implementation considerations. Computation structures are introduced as a means of modeling the dynamic behavior of a software architecture. Functional completeness, quality, machine independence, and performance completeness of a design are then used as criteria for engineering design decisions. Finally, the basic elements of a system to support the software design process are described. © 1976 IEEE Computer Society. All rights reserved.

关键词： Software design

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Fault-tolerant typed assembly language

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acm sigplan NOTICES 2007年第6期42卷 42-53页

作者： Perry, Frances Mackey, Lester Reis, George A. Ligatti, Jay August, David I. Walker, David Princeton Univ Dept Comp Sci & Elect Engn Princeton NJ 08544 USA Univ S Florida Dept Comp Sci & Comp Engn Tampa FL 33620 USA

A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. Although transient faults do not permanently damage the hardware, they may corrupt computations by altering stored values and signal transfers. In this paper, we propose a new scheme for provably safe and reliable computing in the presence of transient hardware faults. In our scheme, software computations are replicated to provide redundancy while special instructions compare the independently computed results to detect errors before writing critical data. In stark contrast to any previous efforts in this area, we have analyzed our fault tolerance scheme from a formal, theoretical perspective. To be specific, first, we provide an operational semantics for our assembly language, which includes a precise formal definition of our fault model. Second, we develop an assembly-level type system designed to detect reliability problems in compiled code. Third, we provide a formal specification for program fault tolerance under the given fault model and prove that all well-typed programs are indeed fault tolerant. In addition to the formal analysis, we evaluate our detection scheme and show that it only takes 34% longer to execute than the unreliable version.

关键词： languages reliability theory verification transient hardware faults soft faults fault tolerance type systems typed assembly language

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An expressive aspect language for system applications with Arachne 05

An expressive aspect language for system applications with A...

引用

AOSD 2005: 4th International conference on Aspect-Oriented Software Development

作者： Douence, Rémi Fritz, Thomas Loriant, Nicolas Menaud, Jean-Marc Ségura-Devillechaise, Marc Südholt, Mario OBASCO Project E ´Cole des Mines de Mantes INRIA 4 rue Alfred Kastler 44307 Nantes Cedex 3 France

ISBN: (纸本)1595930434

C applications, in particular those using operating system level services, frequently comprise multiple crosscutting concerns: network protocols and security are typical examples of such concerns. While these concerns can partially be addressed during design and implementation of an application, they frequently become an issue at runtime, e.g., to avoid server downtime. A deployed network protocol might not be efficient enough and may thus need to be replaced. Buffer overflows might be discovered that imply critical breaches in the security model of an application. A prefetching strategy may be required to enhance performance. While aspect-oriented programming seems attractive in this context, none of the current aspect systems is expressive and efficient enough to address such concerns. This paper presents a new aspect system to provide a solution to this problem. While efficiency considerations have played an important part in the design of the aspect language, the language allows aspects to be expressed more concisely than previous approaches. In particular, it allows aspect programmers to quantify over sequences of execution points as well as over accesses through variable aliases. We show how the former can be used to modularize the replacement of network protocols and the latter to prevent buffer overflows. We also present an implementation of the language as an extension of Arachne, a dynamic weaver for C applications. Finally, we present performance evaluations supporting that Arachne is fast enough to extend high performance applications, such as the Squid web cache. Copyright 2005 acm.

关键词： Software engineering

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Scalable cross-module optimization 98

Scalable cross-module optimization

引用

proceedings of the acm sigplan 1998 conference on programming language design and implementation

作者： Andrew Ayers Stuart de Jong John Peyton Richard Schooler Hewlett-Packard Massachusetts Language Laboratory 300 Apollo Drive Chelmsford MA

ISBN: (纸本)9780897919876

Large applications are typically partitioned into separately compiled modules. Large performance gains in these applications are available by optimizing across module boundaries. One barrier to applying crossmodule optimization (CMO) to large applications is the potentially enormous amount of time and space consumed by the optimization *** describe a framework for scalable CMO that provides large gains in performance on applications that contain millions of lines of code. Two major techniques are described. First, careful management of in-memory data structures results in sub-linear memory occupancy when compared to the number of lines of code being optimized. Second, profile data is used to focus optimization effort on the performance-critical portions of applications. We also present practical issues that arise in deploying this framework in a production environment. These issues include debuggability and compatibility with existing development tools, such as make. Our framework is deployed in Hewlett-Packard's (HP) UNIX compiler products and speeds up shipped independent software vendors' applications by as much as 71%.

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