There are two trends in the software initiatives of the U. S. Department of Defense which will have direct impact on future software development and which suggest a focus for current basic research in software. These ...
ISBN:
(纸本)9780897912181
There are two trends in the software initiatives of the U. S. Department of Defense which will have direct impact on future software development and which suggest a focus for current basic research in software. These trends are 1) the move toward smart weapons, suggesting the use of Expert Systems to control these weapons, and 2) the directive that all software for embedded computer systems be written in Ada. The research focus suggested by these developments is an analysis of the Ada programminglanguage and its associated programming support environment (APSE) to determine how to design and construct an Expert System for natural implementation in *** is well known that Ada can be used as a language for Expert Systems. There now exist several Expert System Shells written in Ada and more are being developed every day. The issue still open to research is how to do this optimally, making the best use of the expressive power of the language. An absurd example will make this clearer. It is also known that it is possible to write an Expert System in COBOL. Doing such would be a very tedious and error prone task, because the expressive power of the COBOL language is focused on commercial *** possibility for writing an Expert System in Ada would be to take an existing Expert System in LISP and translate the code, line for line into Ada. Admittedly this is a plausible task; this author has done some preliminary investigation in this area. However, it is arguable that such an approach will not result in efficient Ada code, for constructs which are natural to LISP might not translate into constructs natural to *** it is difficult to give a precise definition of an Expert System, it is easy to list characteristics which are usually associated with such a system. This paper presents the results of some preliminary research on the implementation of these features by means of some of the structures in Ada, such as Generic Program Units, Packages and Data
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware d...
ISBN:
(纸本)9780769514413
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.
Summary form only given, as follows. We find ASIC technology in a wide variety of demanding applications where high performance, low power, small weight or low parts count is a driving factor in design. This session h...
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Summary form only given, as follows. We find ASIC technology in a wide variety of demanding applications where high performance, low power, small weight or low parts count is a driving factor in design. This session has six articles describing a wide set of diverse applications. We begin with three articles describing ASICs for industrial applications. The first work describes a precision scale controller tha1 increases position resolution by an order of magnitude over existing methodologies. The second work describes a 32 bit embedded SPARC microcontroller designed for high performance motor control. The third details the utilization of a compact neural net design for precisely controlling electrical motor current. The forth work describes FPGA implementation of a Java processor designed to speed up applications v ritten in the popular Java programminglanguage. The FPGA implementation is flexible, allowing the update of the processor design as the Java specification evolves. The fifth article describes the memory architecture of a high performance reconfigurable ATM switch supporting advanced features such as backpressure. The sixth pap r describes an ASIC implementation of the IDEA encryption algorithm. The authors describe an implementation that takes advantage of both temporal and spatial parallelism available in the IDEA algorithm. The HiPCrypto ASIC can encrypt/decrypt data at rates of up to 4.4 Gbps.
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persiste...
ISBN:
(纸本)9780897915922
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persistent on disk or can reside in main-memory. We describe the architecture and implementation of *** were two important goals in the design of the CORAL architecture: (1) to integrate the different evaluation strategies in a reasonable fashion, and (2) to allow users to influence the optimization techniques used so as to exploit the full power of the CORAL implementation. A CORAL declarative program can be organized as a collection of interacting modules and this modular structure is the key to satisfying both these goals. The high level module interface allows modules with different evaluation techniques to interact in a transparent fashion. Further, users can optionally tailor the execution of a program by selecting from among a wide range of control choices at the level of each *** also has an interface with C++, and users can program in a combination of declarative CORAL, and C++ extended with CORAL primitives. A high degree of extensibility is provided by allowing C++ programmers to use the class structure of C++ to enhance the CORAL implementation.
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation pro...
ISBN:
(纸本)9798350369663
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation processes and process-oriented primitives. The flexible modular design of RustSim allows users to extend its functionality. In addition, RustSim includes mechanisms to avoid inconsistencies when applying state-changing primitives that other libraries in the language's ecosystem do not provide. We take advantage of Rust generators (coroutine equivalents) to implement process-oriented simulation primitives. Finally, the library's internal process handling structure is discussed in detail, including its implementation, how simulations are executed, and a case study with a highly detailed example of its use.
Test-cases play an important role for high quality of software testing. Inadequate test-cases may cause bugs remaining after testing. Overlapped ones lead to the increases in testing costs. This paper proposes the Eve...
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Test-cases play an important role for high quality of software testing. Inadequate test-cases may cause bugs remaining after testing. Overlapped ones lead to the increases in testing costs. This paper proposes the Event InterActions Graph (EIAG) representing behavior of concurrent programs including any task-type and the cooperated paths (copaths) on the EIAG as test-cases, and describes the test-case generation tool (TCgen) for concurrent programs written in Ada programminglanguage. The EIAG consists of Event Graphs and Interactions. An Event Graph is a control flow graph of a program unit in a concurrent program. The interactions represent interactions such as synchronizations between the program units. TCgen generates test-cases as copaths from an Ada concurrent program. The generated copaths satisfy given testing criteria. They can find some communication errors in testing and detecting unreachable statements which concern interactions. It is, however, necessary to validate feasibility of the generated copaths.
High quality software components require a representation that allows the implementation-independent description of the structure and behavior of software components. Hence, the static as well as the dynamic structure...
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High quality software components require a representation that allows the implementation-independent description of the structure and behavior of software components. Hence, the static as well as the dynamic structure of the system has to be represented in a structured way. Graph transformation systems support static and dynamic modeling through a single computational framework for the sake of correctness, maintainability, and integrity. The framework introduced along with the corresponding tool, UPGraDE (Universal Programmed Graph Grammar Development Environment), which is based on the universal graph language GRASP (GRAph grammar with Set Productions). Any type of system can be specified through a minimal set of operations (syntax) and rules to specify the behavior of any type of software (semantics). The UPGraDE Environment, consisting of several totally transparent interconnected modules, performing well defined tasks, is a highly modular and extensible environment suited for nearly every GRASP development purpose.
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