Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware d...
ISBN:
(纸本)9780769514413
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.
Aphasia is an acquired communication deficit that impacts the different language modalities. PDAs have a form factor and feature set that suggest they could be effective communication tools for people with aphasia. An...
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ISBN:
(纸本)9781581139112
Aphasia is an acquired communication deficit that impacts the different language modalities. PDAs have a form factor and feature set that suggest they could be effective communication tools for people with aphasia. An ethnographic study was conducted with one participant both to learn about communication strategies used by people with aphasia, and to observe how a PDA is incorporated into those strategies. The most significant usability issues found were file access and organization. A participatory design phase followed, resulting in a paper prototype of a file management system that addressed the key usability issues identified. The participatory approach continued during the implementation of a high-fidelity prototype.
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persiste...
ISBN:
(纸本)9780897915922
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persistent on disk or can reside in main-memory. We describe the architecture and implementation of *** were two important goals in the design of the CORAL architecture: (1) to integrate the different evaluation strategies in a reasonable fashion, and (2) to allow users to influence the optimization techniques used so as to exploit the full power of the CORAL implementation. A CORAL declarative program can be organized as a collection of interacting modules and this modular structure is the key to satisfying both these goals. The high level module interface allows modules with different evaluation techniques to interact in a transparent fashion. Further, users can optionally tailor the execution of a program by selecting from among a wide range of control choices at the level of each *** also has an interface with C++, and users can program in a combination of declarative CORAL, and C++ extended with CORAL primitives. A high degree of extensibility is provided by allowing C++ programmers to use the class structure of C++ to enhance the CORAL implementation.
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation pro...
ISBN:
(纸本)9798350369663
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation processes and process-oriented primitives. The flexible modular design of RustSim allows users to extend its functionality. In addition, RustSim includes mechanisms to avoid inconsistencies when applying state-changing primitives that other libraries in the language's ecosystem do not provide. We take advantage of Rust generators (coroutine equivalents) to implement process-oriented simulation primitives. Finally, the library's internal process handling structure is discussed in detail, including its implementation, how simulations are executed, and a case study with a highly detailed example of its use.
Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property, requirements for adapting existin...
ISBN:
(纸本)9780769518701
Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property, requirements for adapting existing Ips with new services, all stress high-level design as a prominent research topics and call for the development of appropriate methodological solutions. In this aim, system design based on the so-called "synchronous hypothesis" consists of abstracting the non-functional implementation details of a system away and let one benefit from a focused reasoning on the logics behind the instants at which the system functionalities should be secured. From this point of view, synchronous design models and languages provide intuitive models for integrated circuits. This affinity explains the ease of generating synchronous circuits and verify their functionalities using compilers and related tools that implement this approach. In the relational model of the Signal/Polychrony designlanguage/plateform [3, 5] this afffinity goes beyond the domain of purely synchronous circuits to embrace the context of architectures consisting of synchronous circuits and desynchronization protocols: Gals architectures. The unique features of this model are to provide the notion of polychrony: the capability to describe multi-clocked (or partially clocked) circuits and systems; and to support formal design refinement, from the early stages of requirements specification, to the later stages of synthesis and deployment, and by using formal verification techniques.
In this paper, we present the design and implementation of the VRML97 Distributed Authoring Interface (DAI) introduced in Spin-3D, a distributed Collaborative Virtual Environment (CVE). Our proposal is a powerful inte...
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ISBN:
(纸本)9781581136449
In this paper, we present the design and implementation of the VRML97 Distributed Authoring Interface (DAI) introduced in Spin-3D, a distributed Collaborative Virtual Environment (CVE). Our proposal is a powerful interface, very close to the classical VRML97 External Authoring Interface (EAI). The DAI allows the connection of any external application with the Spin-3D CVE platform. With the Spin-3D CVE platform and the DAI, it will be easy to develop collaborative applications. We use the Common Object Request Broker Architecture (CORBA) to support distributed authoring applications. Complex collaborative applications and remote interaction introduce new considerations in the design of the DAI: we enhance the standard VRML97 EAI with new interfaces in order to easily traverse the VRML97 scene graph and limit the network overhead introduced by the remote interaction. Moreover, taking advantage of the CORBA middleware, external applications can be written with any programminglanguage for which the OMG de ned an IDL mapping.
Binary code injection into an executing program is a common form of attack. Most current defenses against this form of attack use a 'guard all doors' strategy, trying to block the avenues by which execution ca...
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ISBN:
(纸本)9781581137385
Binary code injection into an executing program is a common form of attack. Most current defenses against this form of attack use a 'guard all doors' strategy, trying to block the avenues by which execution can be diverted. We describe a complementary method of protection, which disrupts foreign code execution regardless of how the code is injected. A unique and private machine instruction set for each executing program would make it difficult for an outsider to design binary attack code against that program and impossible to use the same binary attack code against multiple machines. As a proof of concept, we describe a randomized instruction set emulator (RISE), based on the open-source Valgrind x86-to-x86 binary translator. The prototype disrupts binary code injection attacks against a program without requiring its recompilation, linking, or access to source code. The paper describes the RISE implementation and its limitations, gives evidence demonstrating that RISE defeats common attacks, considers how the dense x86 instruction set affects the method, and discusses potential extensions of the idea.
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