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Dynamic module replacement in distributed protocols

Dynamic module replacement in distributed protocols

引用

International conference on Distributed Computing Systems

作者： N. Sridhar S.M. Pike B.W. Weide Computer and Information Science Ohio State Uinversity Columbus OH USA

Dynamic module replacement - the ability to hot swap a component's implementation at runtime - is fundamental to supporting evolutionary change in long-lived and highly-available systems. Most existing solutions require special-purpose middleware or depend on research languages with limited support for mainstream software development. We present a language-neutral technique for dynamic module replacement using Service Facilities (Serfs) - a pattern-based design strategy for decoupling runtime dependencies. We demonstrate the sufficiency of Serfs with respect to a litmus test of criteria for module replacement. Next, we extend the traditional scope of module replacement to encompass the domain of modules for distributed protocols. We conclude by applying the Serf strategy to illustrate dynamic replacement of mutual exclusion protocols in modules for distributed resource allocation.

关键词： Protocols Runtime programming Java Middleware Testing Resource management Production facilities Information science Banking

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Formal behavioural synthesis of Handel-C parallel hardware implementations from functional specifications

Formal behavioural synthesis of Handel-C parallel hardware i...

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Annual Hawaii International conference on System Sciences (HICSS)

作者： A.E. Abdallah J. Hawkins South Bank University London UK

Enormous improvements in efficiency can be achieved through exploiting parallelism and realizing implementation in hardware. On the other hand, conventional methods for achieving these improvements are traditionally costly, complex and error prone. Two significant advances in the past decade have radically changed these perceptions. Firstly, the FPGA, which gives us the ability to reconfigure hardware through software, dramatically reducing the costs of developing hardware implementations. Secondly, the language Handel-C with primitive explicit parallelism which can compile programs down to an FPGA. In this paper, we build on these recent technological advances and present a systematic approach of behavioural synthesis. Starting with an intuitive high level functional specification of a problem, given without annotation of parallelism, the approach aims at deriving an efficient parallel implementation in Handel-C, which is subsequently compiled into a circuit implemented on reconfigurable hardware. Algebraic laws are systematically used for exposing implicit parallelism and transforming the specification into a collection of interacting components. Formal methods based on data refinement and a small library of higher order functions are then used to derive behavioural description in Handel-C of each component. A small case study illustrates the use of this approach.

关键词： Hardware Field programmable gate arrays Costs Algorithm design and analysis Circuit synthesis Application software High level languages programming profession Art Functional programming

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Adaptable architectural middleware for programming-in-the-small-and-many 03

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proceedings of the acm/IFIP/USENIX 2003 International conference on Middleware

作者： Marija Mikic-Rakic Nenad Medvidovic University of Southern California Los Angeles CA

ISBN: (纸本)9783540403173

A recent emergence of small, resource-constrained, and highly-mobile computing platforms presents numerous new challenges for software developers. We refer to development in this new setting as programming-in-the-small-and-many (Prism). This paper provides a description and evaluation of a middleware intended to support software architecture-based development in the Prism setting. The middleware, called Prism-MW, provides highly efficient and scalable implementation-level support for the key aspects of Prism application architectures. Additionally, Prism-MW is easily extensible to support different application requirements suitable for the Prism setting. Prism-MW is accompanied with design, analysis, deployment, and run-time monitoring tool support. It has been applied in a number of applications and used as an educational tool in a graduate-level embedded systems course. Recently, Prism-MW has been successfully evaluated by a major industrial organization for use in one of their key distributed embedded systems. Our experience with the middleware indicates that the principles of architecture-based software development can be successfully, and flexibly, applied in the Prism setting.

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The ethnographically informed participatory design of a PD application to support communication 04

The ethnographically informed participatory design of a PD a...

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proceedings of the 6th international acm SIGACCESS conference on Computers and accessibility

作者： Rhian Davies Skip Marcella Joanna McGrenere Barbara Purves University of British Columbia Vancouver BC

ISBN: (纸本)9781581139112

Aphasia is an acquired communication deficit that impacts the different language modalities. PDAs have a form factor and feature set that suggest they could be effective communication tools for people with aphasia. An ethnographic study was conducted with one participant both to learn about communication strategies used by people with aphasia, and to observe how a PDA is incorporated into those strategies. The most significant usability issues found were file access and organization. A participatory design phase followed, resulting in a paper prototype of a file management system that addressed the key usability issues identified. The participatory approach continued during the implementation of a high-fidelity prototype.

关键词： participatory design universal usability assistive technology augmentative alternative communication cognitive disabilities ethnography aphasia handheld devices

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Polychrony for Refinement-Based design 03

Polychrony for Refinement-Based Design

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proceedings of the conference on design, Automation and Test in Europe - Volume 1

作者： Jean-Pierre Talpin Paul Guernic Sandeep Kumar Shukla Rajesh Gupta Frederic Doucet Inria/Irisa Virgina Tech University of California at San Diego

ISBN: (纸本)9780769518701

Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property, requirements for adapting existing Ips with new services, all stress high-level design as a prominent research topics and call for the development of appropriate methodological solutions. In this aim, system design based on the so-called "synchronous hypothesis" consists of abstracting the non-functional implementation details of a system away and let one benefit from a focused reasoning on the logics behind the instants at which the system functionalities should be secured. From this point of view, synchronous design models and languages provide intuitive models for integrated circuits. This affinity explains the ease of generating synchronous circuits and verify their functionalities using compilers and related tools that implement this approach. In the relational model of the Signal/Polychrony design language/plateform [3, 5] this afffinity goes beyond the domain of purely synchronous circuits to embrace the context of architectures consisting of synchronous circuits and desynchronization protocols: Gals architectures. The unique features of this model are to provide the notion of polychrony: the capability to describe multi-clocked (or partially clocked) circuits and systems; and to support formal design refinement, from the early stages of requirements specification, to the later stages of synthesis and deployment, and by using formal verification techniques.

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VRML97 distributed authoring interface 03

VRML97 distributed authoring interface

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proceedings of the eighth international conference on 3D Web technology

作者： Stéphane Louis Dit Samuel Degrande Christophe Gransart Christophe Chaillou Grégory Saugis Université des Sciences et Technologies de Lille LIFL - CNRS UMR 8022 59655 Villeneuve d'Ascq cedex France France

ISBN: (纸本)9781581136449

In this paper, we present the design and implementation of the VRML97 Distributed Authoring Interface (DAI) introduced in Spin-3D, a distributed Collaborative Virtual Environment (CVE). Our proposal is a powerful interface, very close to the classical VRML97 External Authoring Interface (EAI). The DAI allows the connection of any external application with the Spin-3D CVE platform. With the Spin-3D CVE platform and the DAI, it will be easy to develop collaborative applications. We use the Common Object Request Broker Architecture (CORBA) to support distributed authoring applications. Complex collaborative applications and remote interaction introduce new considerations in the design of the DAI: we enhance the standard VRML97 EAI with new interfaces in order to easily traverse the VRML97 scene graph and limit the network overhead introduced by the remote interaction. Moreover, taking advantage of the CORBA middleware, external applications can be written with any programming language for which the OMG de ned an IDL mapping.

关键词： Common Object Request Broker Architecture (CORBA) Collaborative Virtual Environment (CVE) Virtual Reality Modeling language (VRML) External Application Interface (EAI)

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Randomized instruction set emulation to disrupt binary code injection attacks 03

Randomized instruction set emulation to disrupt binary code ...

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proceedings of the 10th acm conference on Computer and communications security

作者： Elena Gabriela Barrantes David H. Ackley Stephanie Forrest Trek S. Palmer Darko Stefanovic Dino Dai Zovi University of New Mexico

ISBN: (纸本)9781581137385

Binary code injection into an executing program is a common form of attack. Most current defenses against this form of attack use a 'guard all doors' strategy, trying to block the avenues by which execution can be diverted. We describe a complementary method of protection, which disrupts foreign code execution regardless of how the code is injected. A unique and private machine instruction set for each executing program would make it difficult for an outsider to design binary attack code against that program and impossible to use the same binary attack code against multiple machines. As a proof of concept, we describe a randomized instruction set emulator (RISE), based on the open-source Valgrind x86-to-x86 binary translator. The prototype disrupts binary code injection attacks against a program without requiring its recompilation, linking, or access to source code. The paper describes the RISE implementation and its limitations, gives evidence demonstrating that RISE defeats common attacks, considers how the dense x86 instruction set affects the method, and discusses potential extensions of the idea.

关键词： emulation obfuscation information hiding security language randomization automated diversity

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proceedings of the acm sigplan conference on programming language design and implementation (PLDI): Foreword

Proceedings of the ACM SIGPLAN Conference on Programming Lan...

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acm sigplan'01 conference on programming language design and implementation (PLDI)

作者： Soffa, M.L.

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proceedings of the acm sigplan conference on programming language design and implementation (PLDI)

Proceedings of the ACM SIGPLAN conference on programming lan...

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acm sigplan'01 conference on programming language design and implementation (PLDI)

The proceedings contains 30 papers from the proceedings of the acm sigplan conference on programming language and implementation (PLDI). Topics discussed include: design and implementation of generics for the .NET common language runtime;dynamic software updating;demand-driven pointer analysis;incrementalized pointer and escape analysis;enforcing high-level protocols in low-level software;language support for regions;principled scavenging;heap profiling for space-efficient Java;composing high-performance memory allocators;and the pointer assertion logic engine.

关键词： Computer programming languages

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MaJIC:: Compiling MATLAB for speed and responsiveness 02

MaJIC:: Compiling MATLAB for speed and responsiveness

引用

conference on programming language design and implementation (PLDI 02)

作者： Almási, G Padua, D Univ Illinois Dept Comp Sci Champaign IL 60680 USA

ISBN: (纸本)9781581134636

This paper presents and evaluates techniques to improve the execution performance of MATLAB. Previous efforts concentrated on source to source translation and batch compilation;MaJIC provides an interactive frontend that looks like MATLAB and compiles/optimizes code behind the scenes in real time, employing a combination of just-in-time and speculative ahead-of-time compilation. Performance results show that the proper mixture of these two techniques can yield near-zero response time as well as performance gains previously achieved only by batch compilers.

关键词： design languages algorithms performance

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