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Evolution of data management systems: from uni-processor to large-scale distributed systems 12

Evolution of data management systems: from uni-processor to ...

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proceedings of the 10th International Conference on advances in Mobile computing & Multimedia

作者： Abdelkader Hameurlain Paul Sabatier University Toulouse Cedex France

ISBN: (纸本)9781450313070

The purpose of this talk is to provide a comprehensive state of the art concerning the evolution of data management systems from uni-processor systems to large scale distributed systems. We focus our study on the query processing and optimization methods. For each environment, we recall their motivations and point out main characteristics of proposed methods, especially, the nature of decision-making (centralized or decentralized control for high level of scalability), adaptive level (intra-operator and/or inter-operator), impact of parallelism (partitioned and pipelined parallelism) and dynamicity (e.g. elasticity) of execution models.

关键词： query processing and optimization parallel and distributed database systems P2P systems heterogeneity data grid systems relational database systems data management autonomy data integration systems large scale dynamicity mobile agents

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Development of the p-medicine oncosimulator as a parallel treatment support system

Development of the p-medicine oncosimulator as a parallel tr...

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International Advanced Research Workshop on In Silico Oncology and Cancer Investigation (IARWISOCI)

作者： Marek Blazewicz Eleni Ch. Georgiadi Juliusz Pukacki Georgios S. Stamatakos Applications Department Poznan Supercomputing & Networking Center Poznan Poland Poznan University of Technology Poznan Poland In Silico Oncology and In Silico Medicine Group National Technical University of Athens Athens Greece

The purpose of this research was the parallelization of the Wilms' Oncosimulator, an integrated cancer treatment support system modeling the growth of nephroblastoma tumors and their in vivo response to chemotherapeutic modalities. In this concept, the Oncosimulator has been optimized in order to perform efficient computations on the newest heterogeneous parallel architectures: the CPU and GPU based computing architectures. The simulator has been implemented using a novel solution for distributed computing on heterogeneous architectures - the Cactus computational toolkit with CaKernel as the module for the computations performed on computing accelerators. In this publication the challenges faced during the process of porting the Oncosimulator onto the aforementioned architectures (within CaKernel framework) are addressed, and the performance benefits of such approaches are analyzed. The successful parallelization of the Oncosimulator advances its computational efficiency and enhances its reusability as well as its eventual translation into clinical practice. The research was performed in the context of the p-medicine project*.

关键词： Biomedical imaging Graphics processing units Acceleration Europe Computer architecture Vectors Programmable logic arrays

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Auction-Based Job Scheduling for Smart Manufacturing 17

Auction-Based Job Scheduling for Smart Manufacturing

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17th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2023

作者： Gatial, Emil Balogh, Zoltan Dolatabadi, Sepideh Hassankhani Ghorbel, Hatem Carrino, Stefano Dreyer, Jonathan Montequin, Vicente Rodriguez Gligor, Adrian Iantovics, Laszlo Barna Institute of Informatics Sav Parallel and Distributed Computing Bratislava Slovakia Institute of Informatics Sav Modelling and Control of Discrete Processes Bratislava Slovakia Haute École Arc Ingénierie HES-SO St-Imier Switzerland University of Oviedo Project Engineering Area Oviedo Spain University of Medicine Pharmacy Science and Technology of Targu Mures Electrical Engineering and Information Technology 'George Emil Palade' Targu Mures Romania

ISBN: (纸本)9798350321104

The paper describes a real-time job scheduling method designed for production of goods with different characteristics on machines with different processing parameters. The objective is to maximize the global reward of the factory as a sum of the rewards for each machine job. Traditionally, the task assignment problems deal with the assignment of m-tasks to n-agents and are calculated by analytical methods or heuristics. The proposed method is based on online auctions that distributes the tasks to the machines using the software agents. The method is implemented using the ERTS (Erlang Real-Time System) that allows adopting the features of fault-tolerance and real-time processing. The paper starts with introduction and review of related state-of-the-art. The following chapter briefly describes the problem and the specific requirements. The following chapter describes the software architecture of the online auction system, the use-case and the motivation for developing this method. The proposed method auction-based task assignment and its implementation are described in the next chapters. At the end of the work, the results of the method are presented in comparison with the optimal solution and the performance characteristics are also described. In the conclusion, possible advances and future work are proposed. © 2023 IEEE.

关键词： Fault tolerance

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7th Workshop on Challenges for parallel computing 12

7th Workshop on Challenges for Parallel Computing

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proceedings of the 2012 Conference of the Center for Advanced Studies on Collaborative Research

作者： Priya Unnikrishnan Kit Barton Tom Chen IBM Canada Software Lab

Over the last decade, interest in parallel programming has grown tremendously. Hardware systems that contain many different levels of parallelism have become mainstream. At one end of the spectrum, computer system that contain many processing cores, each capable of running multiple hardware threads, are becoming commonplace. It is common to find laptop and desktop systems that contain a small number (2--8) of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems can now contain hundreds of these SMP chips, resulting in machines capable of running more than 1000 hardware threads simultaneously. As processor speed begins to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum, as commodity hardware prices fall, it is becoming increasingly affordable to build large-scale multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of about 400,000 cores running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism provided by the thousands of processors they *** types of heterogeneous parallel computing system have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units to maximize their utilization, based on their capabilities. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing hardware in new and novel ways. Others still are

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8th Workshop on Challenges for parallel computing 13

8th Workshop on Challenges for Parallel Computing

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proceedings of the 2013 Conference of the Center for Advanced Studies on Collaborative Research

作者： Priya Unnikrishnan Kit Barton Jeremy Bradbury Reza Azimi IBM Canada Software Lab University of Ontario Institute of Technology

Over the last decade, interest in parallel programming has grown tremendously. Hardware systems that contain many different levels of parallelism have become mainstream. At one end of the spectrum, computer system that contain many processing cores, each capable of running multiple hardware threads, are becoming commonplace. It is common to find laptop and desktop systems that contain a small number of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems can now contain hundreds of these SMP chips, resulting in machines capable of running an incredibly large number of hardware threads simultaneously. As processor speeds begin to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum, as commodity hardware prices fall it is becoming increasingly affordable to build large-scale multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of about 400,000 cores running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism provided by the thousands of processors they *** types of heterogeneous parallel computing system have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units to maximize their utilization, based on their capabilities. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing hardware in new and novel ways. Others sti

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Challenges for parallel computing 11

Challenges for parallel computing

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proceedings of the 2011 Conference of the Center for Advanced Studies on Collaborative Research

作者： Kit Barton Amy Wang Steven Perron Priya Unnikrishnan IBM Canada Ltd.

Over the last decade, interest in parallel programming has grown tremendously and hardware systems that contain different levels of parallelism have become mainstream. At one end of the spectrum, computer systems that contain many processing cores and are each capable of running multiple hardware threads are also becoming commonplace. It is common to find laptop and desktop systems that contain a small number (2--8) of these Shared-Memory Processor (SMP) chips. Furthermore, high-end computing systems are now able to contain hundreds of these SMP chips, resulting in machines that are capable of running more than 1000 hardware threads simultaneously. As processor speeds begin to stagnate, software developers are being forced to exploit the parallelism that is available in these systems in order to improve the performance of their *** the other end of the spectrum and as commodity hardware prices fall, it is becoming increasingly affordable to build large-scale, multi-node distributed machines. A survey of the top 10 supercomputers in the world (***) shows that the systems contain an average of 182,035 processors running at an average frequency of 2.5GHz. Since the average clock frequency of these machines is fairly low, the full potential of these systems must be exploited through efficient use of the parallelism that is provided by the thousands of processors they *** types of heterogeneous parallel computing systems have begun to emerge. These systems contain multiple types of processors - typically a powerful CPU core and some type of Graphics Processing Unit (GPU) or hardware accelerator unit. This type of heterogeneous system provides a new set of challenges for software developers in terms of how to distribute work among the different units based on their capabilities in order to maximize their utilization. Many advances in heterogeneous system design are still being realized as people continue to explore how to combine existing ha

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Multi-modal interaction in the age of information appliances

Multi-modal interaction in the age of information appliances

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IEEE International Conference on Multimedia and Expo (ICME)

作者： S.H. Maes T.V. Raman IBM Thomas J. Watson Research Center USA

The coming millennium will be characterized by the availability of multiple information appliances that make ubiquitous information access an accepted fact of life. The ability to access and transform information via a multiplicity of appliances, each designed to suit the user's specific usage environment, requires the exploitation of all available input and output modalities to maximize the band-width of man-machine communication. There will be an increasingly strong demand for devices that present the same set of functionalities when accessing and manipulating the information, independently of the access device. The resulting uniform interface must be inherently multi-modal and dialog driven. This paper addresses the challenges of coordinated, synchronized multimodal user interaction that is inherent in designing user interfaces that work across these multiplicity of information appliances. Amongst the key issues to be addressed are the user's ability to interact in parallel with the same information via a multiplicity of appliances and user interfaces, and the need to present a unified, synchronized view of information across the various appliances that the user deploys to interact with information. We achieve such synchronized interactions and views by adopting the well-known Model, View, Controller (MVC) design paradigm and adapting it to conversational interactions. The resulting conversational MVC (CMVC) is to be considered as the key underlying principle of any conversational multi-modal application.

关键词： Home appliances Man machine systems Pervasive computing User interfaces Computer networks distributed computing Telephony HTML Computer network management IP networks

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GriT: a CORBA-based grid middleware architecture

GriT: a CORBA-based grid middleware architecture

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： A.S. Gokhale B. Natarajan Institute for Software Integrated Systems Vanderbilt University Nashville TN USA

Rapid advances in networking, hardware, and middleware technologies are facilitating the development and deployment of grid applications, which are characterized, by their very high computing and resource requirements. These applications and services have multiple, simultaneous end-to-end quality of service (QoS) requirements, such as delay guarantees, jitter guarantees, security, scalability, reliability and availability guarantees, and bandwidth and throughput guarantees. Moreover, these applications and services require secure, controlled, reliable, and guaranteed access to different types of resources, such as network bandwidth, computing power, and storage capabilities, available from multiple service providers. To support next-generation grid applications effectively, there is a need to simplify grid programming by developing a new grid middleware that raises the level of abstraction, and reduces the accidental complexities incurred, by programming at the grid infrastructure middleware level offered by existing grid middleware such as Globus, ICENI, and Legion. Moreover, the new grid middleware must ensure multiple end-to-end QoS properties simultaneously. The paper provides three contributions to the research on next generation grid middleware architecture that provides the above-mentioned properties. First, we describe how we are utilizing the standards-based CORBA distributed object computing and integration technology to design the next generation grid middleware, called Grid TAO (GriT) that complements and enhances existing low-level Grid middleware, such as Globus. Second, we describe how we are using the real-time, fault-tolerant, and data parallel CORBA features to implement GriT to provide the desired properties. Finally, we show how CORBA's platform and language independence features are used in GriT to resolve the portability and interoperability challenges faced, by current grid applications.

关键词： Middleware Quality of service Computer architecture Computer networks Grid computing Bandwidth Hardware Delay Jitter Scalability

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Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

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proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

The desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. These systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. This new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

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The UCLA AGCM in high performance computing environments 98

The UCLA AGCM in high performance computing environments

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proceedings of the 1998 ACM/IEEE conference on Supercomputing

作者： C. R. Mechoso L. A. Drummond J. D. Farrara J. A. Spahr University of California Los Angeles Los Angeles CA

ISBN: (纸本)9780897919845

General Circulation Models (GCMs) are at the top of the hierarchy of numerical models that are used to study the Earth's climate. To increase the significance of predictions using GCMs requires ensembles of integrations that in turn demand large amounts of computing resources. GCMs codes are particularly difficult to optimize in view of their heterogeneity. In this paper we focus on code optimization for GCMs of the atmosphere (AGCMs), one of the major components of the climate *** this paper, we present our efforts in optimizing the parallel UCLA AGCM code. The UCLA AGCM is a state-of-the-art finite-difference model of the global atmosphere. Our optimization efforts include the implementation of load balancing schemes, new physical parameterizations of atmospheric processes, code restructuring and use of special mathematical functions. At the beginning of this work, the overall execution time of the code was 459 seconds per simulated day in 256 nodes of a CRAY T3D. At present, the same model configuration requires 51 seconds per simulated day in 256 nodes of a CRAY T3E-900, which is approximately 9 times faster. The peak model performance is about 40 GFLOPs on 512 T3E-900 nodes. We present results in support of our conclusion that major advances in our ability to carry out longer and more detailed climate simulations depend primarily upon development of more powerful supercomputers and that code optimization, for a particular computer architecture, and development of more efficient algorithms can be nearly as important.

关键词： code optimization high performance computing scientific computing climate modeling atmospheric model distributed computing

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