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共 3808 条记录，以下是11-20 订阅

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proceedings of the 2018 design, automation and test in europe conference and Exhibition, DATE 2018

Proceedings of the 2018 Design, Automation and Test in Europ...

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2018 design, automation and test in europe conference and Exhibition, DATE 2018

ISBN: (纸本)9783981926316

The proceedings contain 311 papers. The topics discussed include: moDNN: memory optimal DNN training on GPUs;MATIC: learning around errors for efficient low-voltage neural network accelerators;efficient verification of multi-property designs (the benefit of wrong assumptions);symbolic quick error detection using symbolic initial state for pre-silicon verification;HVSM: hardware-variability aware streaming processors' management policy in GPUs;throughput optimization and resource allocation on GPUs under multi-application execution;set variation-aware shared LLC management for CPU-GPU heterogeneous architecture;cyclic locking and memristor-based obfuscation against CyCSAT and inside foundry attacks;TimingCamouflage: improving circuit security against counterfeiting by unconventional timing;advancing hardware security using polymorphic and stochastic spin-hall effect devices;main memory organization trade-offs with dram and STT-MRAM options based on gem5-nvmain simulation frameworks;exploring the opportunity of implementing neuromorphic computing systems with spintronic devices;novel application of spintronics in computing, sensing, storage and cybersecurity;the FED4SAE project, accelerating european cps solutions to market;and transferring research results to safety-relevant products: case study on automated driving software.

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Polynomial Formal Verification of Sequential Circuits

Polynomial Formal Verification of Sequential Circuits

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Dominik, Caroline Drechsler, Rolf Univ Bremen DFKI Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9798350348606;9783981926385

Recently, the concept of Polynomial Formal Verification (PFV) has been introduced and successfully applied to several classes of functions, allowing complete verification under resource constraints. But so far, all studies were carried out for combinational circuits only. In this paper we show how the concept of PFV can be extended to sequential circuits. As a first case study we show for counters that PFV can be performed, even though they have an exponential number of states, i.e., they can be fully formally verified within polynomial upper bounds on run-time and memory requirement.

关键词： circuit design correctness verification test formal methods BDD

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A Novel March test Algorithm for testing 8T SRAM-based IMC Architectures

A Novel March Test Algorithm for Testing 8T SRAM-based IMC A...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Ammoura, Lila Flottes, Marie-Lise Girard, Patrick Noel, Jean-Philippe Virazel, Arnaud LIRMM Univ Montpellier CNRS F-34392 Montpellier France Univ Grenoble Alpes CEA LIST F-38000 Grenoble France

ISBN: (纸本)9798350348606;9783981926385

The shift towards data-centric computing paradigms has given rise to new architectural approaches aimed at minimizing data movement and enhancing computational efficiency. In this context, In-Memory Computing (IMC) architectures have gained prominence for their ability to perform processing tasks within the memory array, reducing the recourse to data transfers. However, the susceptibility of these new paradigms to manufacturing defects poses a critical test challenge. This paper presents a novel March-like test algorithm for 8T SRAM-based IMC architectures, addressing the imperative need for comprehensive read port related defect coverage. The proposed algorithm achieves complete coverage of potential read port defects while maintaining the level of complexity equivalent to existing state-of-the-art test solutions.

关键词： In-Memory Computing 8T SRAM bitcell testing March test algorithm DfT

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proceedings of the 2021 design, automation and test in europe, DATE 2021

Proceedings of the 2021 Design, Automation and Test in Europ...

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2021 design, automation and test in europe conference and Exhibition, DATE 2021

ISBN: (纸本)9783981926354

The proceedings contain 358 papers. The topics discussed include: HyGraph: accelerating graph processing with hybrid memory-centric computing;neighbor oblivious learning (NObLe) for device localization and tracking;parametric throughput oriented large integer multipliers for high level synthesis;PLEDGER: embedded whole genome read mapping using algorithm-HW co-design and memory-aware implementation;hardware redaction via designer-directed fine-grained eFPGA insertion;GEO: generation and execution optimized stochastic computing accelerator for neural networks;TiVaPRoMi: time-varying probabilistic row-hammer mitigation;adaptive design of real-time control systems subject to sporadic overruns;MAVIREC: ML-aided vectored IR-drop estimation and classification;and remote power side-channel attacks on BNN accelerators in FPGAs.

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HDCircuit: Brain-inspired HyperDimensional Computing for Circuit Recognition

HDCircuit: Brain-inspired HyperDimensional Computing for Cir...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Genssler, Paul R. Alrahist, Lilas Sinanoglu, Ozgur Amrouch, Hussam Univ Stuttgart Semicond Test & Reliabil Stuttgart Germany New York Univ Abu Dhabi Abu Dhabi U Arab Emirates Tech Univ Munich Chair AI Processor Design Munich Germany TUM Sch Computat Informat & Technol Munich Germany Munich Inst Robot & Machine Intelligence Munich Germany

ISBN: (纸本)9798350348606;9783981926385

Circuits possess a non-Euclidean representation, necessitating the encoding of their data structure (e.g., gate-level netlists) into fixed formats like vectors. This work is the first to propose brain-inspired hyperdimensional computing (HDC) for optimized circuit encoding. HDC does not require extensive training to encode a gate-level netlist into a hypervector and simplifies the similarity check between circuits from graph-based to the similarity between their hypervectors. We introduce a versatile HDC-based encoding method for circuit encoding. We demonstrate its effectiveness with the application of circuit recognition using ITC-99 and ISCAS-85 benchmarks. We maintain a 98.2% accuracy, even when the designs are obfuscated using logic locking.

关键词： Hyperdimensional computing Circuit encoding Circuit recognition Hardware intellectual property

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An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVM

An Endeavor to Industrialize Hardware Fuzzing: Automating No...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Ma, Ruiyang Zhao, Huatao Huang, Jiayi Zhang, Shijian Luo, Guojie Peking Univ Sch Comp Sci Beijing Peoples R China Alibaba DAMO Acad Comp Technol Lab Hangzhou Peoples R China Hong Kong Univ Sci & Technol Guangzhou Microelect Thrust Guangzhou Peoples R China

ISBN: (纸本)9798350348606;9783981926385

We endeavor to make hardware fuzzing compatible with the standard IC development process and apply that to NoC verification in a real-world industrial environment. We systematically employ fuzzing throughout the entire NoC verification process, including router verification, network verification, and stress testing. As a case study, we apply our approach to an open-source NoC component in OpenPiton. Remarkably, our fuzzing methods automatically achieved complete code and functional coverage in the router and mesh network, and effectively detect injected starvation bugs. The evaluation results clearly demonstrate the practicability of our fuzzing approach to considerably reduce the manpower required for test case generation compared with traditional NoC verification.

关键词： design Verification Hardware Fuzzing Network on Chip Automatic test Generation

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RL-TPG : Automated Pre-Silicon Security Verification through Reinforcement Learning-Based test Pattern Generation

RL-TPG : Automated Pre-Silicon Security Verification through...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Mondol, Nurun Nahar Vafei, Arash Azar, Kimia Zamiri Farahmandi, Farimah Tehranipoor, Mark Univ Florida ECE Gainesville FL 32611 USA

ISBN: (纸本)9798350348606;9783981926385

Verifying the security of System-on-Chip (SoC) designs against hardware vulnerabilities is challenging because of the increasing complexity of SoCs, the diverse sources of vulnerabilities, and the need for comprehensive testing to identify potential security threats. In this paper, we propose RL-TPG, a novel framework that combines traditional verification with hardware security verification using Reinforcement Learning (RL) in Register Transfer Level (RTL) design. Significant research has been done on formal verification, semi-formal verification, automated security asset identification, and gate-level netlist. However, the area of automated simulation using machine learning at RTL is still unexplored. RL-TPG employs an RL agent that generates intelligent test patterns targeting security properties, verification coverage, and rare nodes of the design to achieve security property violation, increase verification coverage, and reach rare nodes. Our framework triggers all embedded vulnerabilities, achieving an average of 90% traditional coverage in an average of 192 seconds for the experimental benchmarks. To demonstrate the effectiveness of the approach, the results are compared with JasperGold by Cadence.

关键词： Reinforcement learning

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Device-Aware Diagnosis for Yield Learning in RRAMs

Device-Aware Diagnosis for Yield Learning in RRAMs

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Xun, Hanzhi Fieback, Moritz Yuan, Sicong Aziza, Hassen Taouil, Mottaqiallah Hamdioui, Said Delft Univ Technol Delft Netherlands Aix Marseille Univ Marseille France CognitiveIC Delft Netherlands

ISBN: (纸本)9798350348606;9783981926385

Resistive Random Access Memories (RRAMs) are now undergoing commercialization, with substantial investment from many semiconductor companies. However, due to the immature manufacturing process, RRAMs are prone to exhibit unique defects, which should be efficiently identified for high-volume production. Hence, obtaining diagnostic solutions for RRAMs is necessary to facilitate yield learning, and improve RRAM quality. Recently, the Device-Aware test (DAT) approach has been proposed as an effective method to detect unique defects in RRAMs. However, the DAT focuses more on developing defect models to aid production testing but does not focus on the distinctive features of defects to diagnose different defects. This paper proposes a Device-Aware Diagnosis method;it is based on the DAT approach, which is extended for diagnosis. The method aims to efficiently distinguish unique defects and conventional defects based on their features. To achieve this, we first define distinctive features of each defect based on physical analysis and characterizations. Then, we develop efficient diagnosis algorithms to extract electrical features and fault signatures for them. The simulation results show the effectiveness of the developed method to reliably diagnose all targeted defects.

关键词： RRAM defects device-aware diagnosis test

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Algorithm to Technology Co-Optimization for CiM-based Hyperdimensional Computing

Algorithm to Technology Co-Optimization for CiM-based Hyperd...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Mayahinia, Mahta Thomann, Simon Genssler, Paul R. Muench, Christopher Amrouch, Hussam Tahoori, Mehdi B. Karlsruhe Inst Technol Dept Comp Sci & Informat Karlsruhe Germany Tech Univ Munich TUM Sch Computat Informat & Technol Chair AI Processor Design Munich Germany Univ Stuttgart Semicond Test & Reliabil Stuttgart Germany

ISBN: (纸本)9798350348606;9783981926385

Hyperdimensional computing (HDC) has been recognized as an efficient machine learning algorithm in recent years. Robustness against noise and simple computational operations, while being limited by the memory bandwidth, make it a perfect fit for the concept of computation in memory (CiM) with emerging nonvolatile memory (NVM) technologies. For an HDC accelerator based on NVM-CiM, there are different parameters from the algorithm all the way down to the technology that interact with each other and affect the overall inference accuracy as well as the energy efficiency of the accelerator. Therefore, in this paper, we propose, for the first time, a full-stack co-optimization method and use it to design an HDC accelerator based on NVM-based content addressable memory (CAM). By incorporating the device manufacturing variability and co-optimizing the algorithm and hardware design, HDC inference on our proposed NVM-based CiM accelerator can reduce the energy consumption by 3.27x, while compared to the purely software-based implementation, the inference accuracy loss is merely 0.125%.

关键词： Hyperdimensional computing Analog computing Non-volatile memory Content addressable memory (CAM)

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PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-time Memory Diagnostic Data Compression in Automotive SoCs

PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-tim...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Park, Sunyoung Kim, Hyunji Kim, Hana Kim, Ji-Hoon Ewha Womans Univ Dept Elect & Elect Engn Seoul South Korea Ewha Womans Univ Grad Program Smart Factory Seoul South Korea

ISBN: (纸本)9798350348606;9783981926385

In the realm of safety-critical Automotive System-on-Chip (SoC) design, memory functionality plays a crucial role in determining overall die yield due to its sizable footprint on the chip. Therefore, efficient methodologies for both post-manufacturing offline testing and real-time monitoring are essential to provide timely diagnostic feedback. This paper proses a real-time memory diagnostic data compression technique Pattern-Adaptive Two-Stage Bloom Filter (PA-2SBF) for automotive System-on-Chip (SoC) applications. PA-2SBF is designed to address the challenge of false positives incorporating frequently encountered failure patterns. Bloom filters, a probabilistic data structure renowned for their space-efficiency and quick approximate membership queries, are employed to expedite fault memory diagnosis information lookup and compression. Furthermore, failure patterns are considered to mitigate the false positive rate inherent in Bloom filters. The paper also presents a strategy for leveraging the compressed diagnostic information during run-time. Specifically, it exploits the quick lookup feature of Bloom filter to prohibit CPU access to defective memory regions, enhancing overall system reliability.

关键词： Memory Diagnosis Automotive SoC Memory testing test Compression Bloom Filter

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