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检索条件"任意字段=Proceedings of the Conference on Design, Automation and Test in Europe"

共 3808 条记录，以下是191-200 订阅

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Evaluating Compiler-Based Reliability with Radiation Fault Injection

Evaluating Compiler-Based Reliability with Radiation Fault I...

引用

design, automation and test in europe conference and Exhibition

作者： Davide Baroffio Tomás Antonio López Federico Reghenzani William Fornaciari Department of Electronics Information and Bioengineering Politecnico di Milano Milan Italy

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Compiler-based fault tolerance is a cost-effective and flexible family of solutions that transparently improves software reliability. This paper evaluates a compiler tool for fault detection via laser injection and α-particle exposure. A novel memory allocation strategy is proposed to mitigate the effects of multi-bit upsets. We integrated the detection mechanism with a recovery solution based on mixed-criticality scheduling. The results demonstrate the error detection and recovery capabilities in realistic scenarios: reducing undetected errors, enhancing system reliability, and advancing software-implemented fault tolerance.

关键词： Fault tolerance Semiconductor lasers Fault detection Fault tolerant systems europe Software reliability Resource management

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Weld Forming of 06Cr19Ni10 Stainless Steel Ring-Stiffened Cylindrical Pressure Shell of UUV 9

Weld Forming of 06Cr19Ni10 Stainless Steel Ring-Stiffened Cy...

引用

9th International conference on Mechanical Engineering, Materials, and automation Technology, MMEAT 2023

作者： Zhang, Laming Liu, Tianjiao Xia, Xiaojiao Tian, Hefei Yu, Haijun Duan, Ziyu Kunming Shipbuilding Equipment Research and Test Center Kunming China

ISBN: (纸本)9781510668584

The pressure shell is a key component to ensure the pressure bearing and sealing of the unmanned underwater vehicle (UUV). Considering the requirements of reliability, economy, and anti-corrosion performance, the weld forming method of 06Cr19Ni10 stainless steel ring-stiffened cylindrical pressure shell was studied. Firstly, according to the existing pressure shell structure, the strength design is carried out with reference to the design code of China Classification Society, and the structural model of the ring-stiffened cylindrical pressure shell is obtained. Then, through the analysis of the weld forming process, the deformation control method of the pressure shell in the manufacturing process is studied, and the weld forming process of the ring-stiffened cylindrical pressure shell is determined. Finally, the weld forming method of 06Cr19Ni10 stainless steel ring-stiffened cylindrical pressure shell is verified through small-batch trial production and external pressure test, which provides a reference for the pressure shell design of the new underwater unmanned underwater vehicle. The external hydraulic test shows that the welding and heat treatment process proposed in this paper can not only ensure the structural strength of the shell, but also effectively control the welding deformation, and ensure the sealing performance of the shell through the final cutting process. © 2023 SPIE.

关键词： Welds

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REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks

REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Le...

引用

design, automation and test in europe conference and Exhibition

作者： Hassan Nassar Ming-Liang Wei Chia-Lin Yang Jörg Henkel Kuan-Hsun Chen Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany National Taiwan University Taiwan University of Twente the Netherlands

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

NVM-based PUFs offer secure authentication and cryptographic applications by exploiting NVMs' MLC to generate diverse, ML-attack-resistant responses. Yet, frequent writes degrade these PUFs, lowering reliability and lifespan. This paper presents a model to assess endurance effects on NVM PUFs, guiding the creation of more robust PUFs. Our novel NVM PUF design enhances endurance by evenly distributing writes, thus mitigating cell stress, achieving a 62x improvement over current solutions while preserving security against learning-based attacks.

关键词： Degradation Nonvolatile memory europe Authentication Predictive models Physical unclonable function Reliability Cryptography Stress

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NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch design with Optimized Overhead

NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch...

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design, automation and test in europe conference and Exhibition

作者： Aibin Yan Wangjin Jiang Han Bao Zhengfeng Huang Tianming Ni Xiaoqing Wen Patrick Girard School of Microelectronics Hefei University of Technology Hefei China School of Integrated Circuits Anhui Polytechnic University Wuhu China Graduate School of Computer Science and Systems Engineering Kyushu Institute of Technology Fukuoka Japan LIRMM University of Montpellier / CNRS Montpellier France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper presents a FeFET-based non-volatile and single-event upset (SEU) recoverable latch, namely NVSRLO, which does not require any extra control signals. Simulation results show that the proposed latch provides non-volatility and SEU-recovery with optimized overhead. Compared with existing non-volatile latches, NVSRLO significantly reduces delay, power, and delay-power-area product at the cost of area.

关键词： Latches Costs Radiation hardening (electronics) Simulation Single event upsets europe Delays Energy harvesting FeFETs

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design AND test OF A CYLINDER MOTION ACTUATOR 3

DESIGN AND TEST OF A CYLINDER MOTION ACTUATOR

引用

3rd International conference on Artificial Intelligence and Electromechanical automation, AIEA 2022

作者： Zhao, Shijie Wang, Wenyun Chen, Zerui Kunming Shipborne Equipment Research and Test Center Kunming650051 China

ISBN: (纸本)9781510657281

A rodless cylinder motion actuator aimed at requirement of small space taken and high reliability motion of a certain project was designed. The design process of scheme, selection of core components, mechanical structure and control circuit were described in detail. A prototype actuator was built and motion tests were carried out. The test result shows that the actuator is stable and reliable, and the motion index meets the design requirements. © 2022 SPIE.

关键词： Cylinders (shapes)

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Late Breaking Results: Energy-Efficient Printed Machine Learning Classifiers with Sequential SVMs

Late Breaking Results: Energy-Efficient Printed Machine Lear...

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design, automation and test in europe conference and Exhibition

作者： Spyridon Besias Ilias Sertaridis Florentia Afentaki Konstantinos Balaskas Georgios Zervakis Department of Computer Engineering & Informatics University of Patras Patras Greece

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Printed Electronics (PE) provide a mechanically flexible and cost-effective solution for machine learning (ML) circuits, compared to silicon-based technologies. However, due to large feature sizes, printed classifiers are limited by high power, area, and energy overheads, which restricts the realization of battery-powered systems. In this work, we design sequential printed bespoke Support Vector Machine (SVM) circuits that adhere to the power constraints of existing printed batteries while minimizing energy consumption, thereby boosting battery life. Our results show 6.5x energy savings while maintaining higher accuracy compared to the state of the art.

关键词： Support vector machines Energy consumption Accuracy Machine learning algorithms Limiting Circuits europe Energy efficiency Hardware Batteries

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RGHT-Q: Reconfigurable GEMM Unit for Heterogeneous-Homogeneous Tensor Quantization

RGHT-Q: Reconfigurable GEMM Unit for Heterogeneous-Homogeneo...

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design, automation and test in europe conference and Exhibition

作者： Seungho Lee Donghyun Nam Jeongwoo Park Dept. of Semiconductor Convergence Engineering Sungkyunkwan University Dept. of Electrical and Computer Engineering Sungkyunkwan University

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The high computational demands of large language models (LLMs) are limited by the lack of GPU hardware support for heterogeneous quantization, which mixes integers and floating points. To address this limitation, we propose an LLM processing element (PE), RGHT-Q, which features reconfigurable general-matrix multiplication (GEMM) operations for both heterogeneous and homogeneous tensor quantization. The RGHT-Q introduces a novel design that leverages butterfly routing and multi-precision multipliers. As a result, we achieve significant performance improvements, offering 3.14× higher energy efficiency, and 1.56× better area efficiency compared to prior designs.

关键词： Quantization (signal) Tensors Large language models Graphics processing units europe Routing Hardware Energy efficiency

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Minimum Time Maximum Fault Coverage testing of Spiking Neural Networks

Minimum Time Maximum Fault Coverage Testing of Spiking Neura...

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design, automation and test in europe conference and Exhibition

作者： Spyridon Raptis Haralampos-G. Stratigopoulos Sorbonne Université CNRS LIP6 Paris France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

We present a novel test generation algorithm for hardware accelerators of Spiking Neural Networks (SNNs). The algorithm is based on advanced optimization tailored for the spiking domain. It adaptively crafts input samples towards high coverage of hardware-level faults. Time-consuming fault simulation during test generation is circumvented by defining loss functions targeting the maximization of fault sensitisation and fault effect propagation to the output. Comparing the proposed algorithm to the existing ones on three benchmarks, it scales up for large SNN models, and it drastically reduces the test generation runtime from days to hours and the test duration from minutes to seconds. The resultant test input shows near perfect fault coverage and has a duration equivalent to a few dataset samples, thus, besides post-manufacturing testing, it is also suited for in-field testing.

关键词： Runtime Neuromorphic engineering Neurons Spiking neural networks Benchmark testing Propagation losses test pattern generators Reliability Optimization Synapses

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AMBEATion: Analog Mixed-Signal Back-End design automation with Machine Learning and Artificial Intelligence Techniques

AMBEATion: Analog Mixed-Signal Back-End Design Automation wi...

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design, automation and test in europe conference and Exhibition

作者： Giulia Elena Aliffi Joao Baixinho Dalibor Barri Francesco Daghero Nicola Di Carolo Gabriele Faraone Michelangelo Grosso Daniele Jahier Pagliari Jiri Jakovenko Vladimír Janíček Dario Licastro Vazgen Melikyan Matteo Risso Vittorio Romano Eugenio Serianni Martin Štastný Patrik Vacula Giorgia Vitanza Chen Xie University of Catania Catania Italy Synopsys Politecnico di Torino Turin Italy STMicroelectronics Czech Technical University Prague Czech Republic

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

For the competitiveness of the european economy, automation techniques in the design of complex electronic systems are a prerequisite for winning the global chip challenge. Specifically, while the physical design of digital Integrated Circuits (ICs) can be largely automated, the physical design of Analog-Mixed-Signal (AMS) ICs built with an analog-on-top flow, where digital subsystems are instantiated as Intellectual Property (IP) modules, is still carried out predominantly by hand, with a time-consuming methodology. The AMBEATion consortium, including global semiconductor and design automation companies as well as leading universities, aims to address this challenge by combining classic Electronic design automation (EDA) algorithms with novel Artificial Intelligence and Machine Learning (ML) techniques. Specifically, the scientific and technical result expected at the end of the project will be a new methodology, implemented in a framework of scripts for AMS placement, internally making use of state-of-the-art AI/ML models, and fully integrated with Industrial design flows. With this methodology, the AMBEATion consortium aims to reduce the design turnaround-time and, consequently, the silicon development costs of complex AMS ICs.

关键词： design automation Machine learning algorithms Costs europe Digital integrated circuits Machine learning Intellectual property

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GRAMC: General-Purpose and Reconfigurable Analog Matrix Computing Architecture

GRAMC: General-Purpose and Reconfigurable Analog Matrix Comp...

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design, automation and test in europe conference and Exhibition

作者： Lunshuai Pan Shiqing Wang Pushen Zuo Zhong Sun Institute for Artificial Intelligence School of Integrated Circuits Peking University Beijing Advanced Innovation Center for Integrated Circuits

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In-memory analog matrix computing (AMC) with resistive random-access memory (RRAM) represents a highly promising solution that solves matrix problems in one step. However, the existing AMC circuits each have a specific connection topology to implement a single computing function, lack of the universality as a matrix processor. In this work, we design a reconfigurable AMC macro for general-purpose matrix computations, which is achieved by configuring proper connections between memory array and amplifier circuits. Based on this macro, we develop a hybrid system that incorporates an on-chip write-verify scheme and digital functional modules, to deliver a general-purpose AMC solver for various applications.

关键词： Circuits europe Computer architecture In-memory computing Topology System-on-chip

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