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检索条件"任意字段=Proceedings of the Conference on Design, Automation and Test in Europe"

共 3808 条记录，以下是231-240 订阅

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Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries

Enabling a Portable Brain Computer Interface for Rehabilitat...

引用

design, automation and test in europe conference and Exhibition

作者： Adrian Evans Victor Roux-Sibillon Joe Saad Ivan Miro-Panades Tetiana Aksenova Lorena Anghel Univ. Grenoble Alpes CEA LIST Grenoble France Univ. Grenoble Alpes CEA LETI Grenoble France Univ. Grenoble Alpes CNRS Grenoble INP Grenoble France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

In clinical trials, brain signal decoders combined with spinal stimulation have shown to be a promising means to restore mobility to paraplegic and tetraplegic patients. To make this technology available for home use, the complex brain signal decoding must be performed using a low-power, portable battery operated system. This case study shows how the decoding algorithm for a Brain-Computer Interface (BCI) system was ported to an embedded platform, resulting in an over 25 x power reduction, compared to the previous implementation, while respecting real-time and accuracy constraints.

关键词： Integrated circuits europe Implants Motors Feature extraction Brain-computer interfaces Real-time systems Decoding Spinal cord injury Optimization

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SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memory Architecture

SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memor...

引用

design, automation and test in europe conference and Exhibition

作者： Yanfeng Yang Yi Zou Zhibiao Xue Liuyang Zhang School of Microelectronics South China University of Technology Guangzhou China National Key Laboratory of Spintronics Hungzhou International Innovation Institute Beihang University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This study introduces HWCIM, a SRAM-based Computing-In-Memory core, and SHWCIM, a CIM-capable Coarse-Grained Reconfigurable Architecture, to enhance re-source utilization, multi-functionality, and on-chip memory size in SRAM-based CIM designs. Evaluated using the SMIC 55nm process, HWCIM achieves 1.6x lower power, 2.8x higher energy efficiency, and up to 4.1x smaller area compared to previous CIM and CGRA works. Additionally, SHWCIM delivers an average 105.9x speedup over existing CGRAs and consumes 2-5x less energy than the Nvidia A40 GPU on realistic workloads.

关键词： Graphics processing units europe In-memory computing Common Information Model (computing) Energy efficiency Vectors System-on-chip Reconfigurable architectures Common Information Model (electricity) Resource management

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A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA

A 10ps-Order Flexible Resolution Time-to-Digital Converter w...

引用

design, automation and test in europe conference and Exhibition

作者： Kentaroh Katoh Toru Nakura Haruo Kobayashi Dept. of Electronics Engineering and Computer Science Faculty of Engineering Fukuoka University Japan Professor Emeritus Gunma Univesity Japan

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper presents a 10ps-order flexible resolution time-to-digital converter (TDC) consisting of only Lookup Tables and Flip-Flops that can be applied to legacy FPGAs, which is industry friendly. The proposed TDC is a Vernier delay-line based TDC. By using MUX chains as the delay adjustable buffers, it realizes flexible and high resolution 10ps-order TDC. By controlling the control values of each MUX chain independently, the nonlinearity of TDC is compensated. In the evaluation using the AMD Artix-7 FPGA, the DNL and INL were [−0.26 LSB, 0.91 LSB] and [−0.84 LSB, 2.27 LSB], respectively, at a resolution of 8.92 ps.

关键词： Industries Linearity europe Hardware Calibration Table lookup Delays Field programmable gate arrays Flip-flops

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Operation Dependency Graph-Based Scheduling for High-Level Synthesis

Operation Dependency Graph-Based Scheduling for High-Level S...

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design, automation and test in europe conference and Exhibition

作者： Aoxiang Qin Minghua Shen Nong Xiao School of Computer Science and Engineering Sun Yat-Sen University Guangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Scheduling determines the execution order and time of operations in program. The order is related to operation dependencies, including data and resource dependencies. Data dependencies are intrinsic in programs, while resource dependencies are determined by scheduling methods. Existing scheduling methods lack an accurate and complete operation dependency graph (ODG), leading to poor performance. In this paper, we propose an ODG-based scheduling method for HLS with GNN and RL. We adopt GNN to perceive accurate relations between operations. We use the relations to guide an RL agent in building a complete ODG. We perform feedback-guided iterative scheduling with the graph to converge to a high-quality solution. Experiments show that our method reduces 23.8% and 16.4% latency on average, compared with the latest GNN-based and RL-based methods, respectively.

关键词： Accuracy Buildings europe Bidirectional control Iterative methods

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PESEC – A Simple Power-Efficient Single Error Correcting Coding Scheme for RRAM

PESEC – A Simple Power-Efficient Single Error Correcting Co...

引用

design, automation and test in europe conference and Exhibition

作者： Shlomo Engelberg Osnat Keren Dept. of Electrical and Electronics Engineering Jerusalem College of Technology Jerusalem Israel Faculty of Engineering Bar-Ilan University Ramat Gan Israel

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The power consumed when writing to Resistive Random Access Memory (RRAM) is significantly greater than that consumed by many charge-based memories such as SRAM, DRAM and NAND-Flash memories. As a result, when used in applications where instantaneous power consumption is constrained, the number of bits that can be set or reset must not exceed a certain threshold. In this paper, we present a power-efficient, single error correcting (PESEC) code for memory macros, which, when combined with bus encoding, ensures low-power operation and reliable data storage. This systematic, multiple-representation based single-error correcting code provides a relatively high rate, with a marginal increase in implementation cost relative to that of a standard Hamming code, and it can be used with any bus encoder.

关键词： Systematics Power demand Nonvolatile memory Resistive RAM europe Writing Encoding Error correction codes Reliability Standards

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EF-IMR: Embedded Flash with Interlaced Magnetic Recording Technology

EF-IMR: Embedded Flash with Interlaced Magnetic Recording Te...

引用

design, automation and test in europe conference and Exhibition

作者： Chenlin Ma Xiaochuan Zheng Kaoyi Sun Tianyu Wang Yi Wang College of Computer Science and Software Engineering Shenzhen University China State Key Laboratory of Radio Frequency Heterogeneous Integration

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Interlaced Magnetic Recording (IMR), a technology that improves storage density through track overlap, introduces significant latency due to Read-Modify-Write (RMW) operations. Writing to overlapped tracks affects underlying tracks, requiring additional I/O operations to read, back up, and rewrite them, resulting in significant head movement latency. We propose EF-IMR, a new architecture that ensures crash consistency in IMR while minimizing RMW latency and head movement. EF-IMR reduces head movement during RMW operations and decreases redundant RMW operations. Evaluations under real-world, intensive I/O workloads show that EF-IMR reduces RMW latency by 20.11 % and head movement latency by 89.37% compared to existing methods.

关键词： Tracking europe Writing Magnetic heads Computer crashes Delays Magnetic recording

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Late Breaking Results: Practical Electromagnetic Fault Injection on Intel Neural Compute Stick 2

Late Breaking Results: Practical Electromagnetic Fault Injec...

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design, automation and test in europe conference and Exhibition

作者： Shivam Bhasin Dirmanto Jap Prasanna Ravi Marina Krček Stjepan Picek National Integrated Centre for Evaluation (NiCE) Nanyang Technological University Singapore Radboud University Nijmegen The Netherlands

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Machine learning (ML) has been widely deployed in various applications, with many applications being in critical infrastructures. One recent paradigm is edge ML, an implementation of ML on embedded devices for Internet-of- Things (IoT) applications. In this work, we have conducted a practical experiment on Intel Neural Compute Stick (NCS) 2, an edge ML device, with regard to fault injection (FI) attacks. More precisely, we have employed electromagnetic fault injection (EMFI) on NCS 2 to evaluate the practicality of the attack on a real target device. We have investigated multiple fault parameters with a low-cost pulse generator, aiming to achieve misclassification at the output of the inference. Our experimental results demonstrated the possibility of achieving practical and repeatable misclassifications.

关键词： Pulse generation Computational modeling europe Machine learning Critical infrastructure Internet of Things Electromagnetics

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CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal Selection

CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN a...

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design, automation and test in europe conference and Exhibition

作者： Tong Liu Zijun Jiang Yangdi Lyu Microelectronics Thrust The Hong Kong University of Science and Technology (Guangzhou)

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Effective power management is crucial for optimizing the performance and longevity of integrated circuits. Cycle-accurate power prediction can help power management during runtime. This paper introduces a Cycle-accurate Power Prediction framework via Spiking neural networks (SNNs) and Genetic signal Selection (CPP-SGS), which integrates SNNs and Genetic Algorithms (GAs) to predict real-time power consumption of chips. We apply GAs to select the most relevant signals as the input to SNNs to reduce the model size and inference time, making it well-suited for dynamic power estimation in real-time scenarios. The experimental results show that CCP-SGS outperforms the state-of-the-art approaches, with a normalized root mean squared error (NRMSE) of less than 1.6%.

关键词： Integrated circuits Power demand Runtime Power system management europe Spiking neural networks Predictive models Genetics Real-time systems Genetic algorithms

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Monomorphism-Based CGRA Mapping Via Space and Time Decoupling

Monomorphism-Based CGRA Mapping Via Space and Time Decouplin...

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design, automation and test in europe conference and Exhibition

作者： Cristian Tirelli Rodrigo Otoni Laura Pozzi Faculty of Informatics Universitá della Svizzera italiana Lugano Switzerland

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Coarse-Grain Reconfigurable Arrays (CGRAs) provide flexibility and energy efficiency in accelerating compute-intensive loops. Existing compilation techniques often struggle with scalability, unable to map code onto large CGRAs. To address this, we propose a novel approach to the mapping problem where the time and space dimensions are decoupled and explored separately. We leverage an SMT formulation to traverse the time dimension first, and then perform a monomorphism-based search to find a valid spatial solution. Experimental results show that our approach achieves the same mapping quality of state-of-the-art techniques while significantly reducing compilation time, with this reduction being particularly tangible when compiling for large CGRAs. We achieve approximately 10 5 × average compilation speedup for the benchmarks evaluated on a 20 × 20 CGRA.

关键词： Codes Scalability europe Benchmark testing Energy efficiency Optimization

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Security Assertions for Trusted Execution Environments

Security Assertions for Trusted Execution Environments

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design, automation and test in europe conference and Exhibition

作者： Hasini Witharana Hansika Weerasena Prabhat Mishra Department of Computer & Information Science & Engineering University of Florida Gainesville Florida USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Trusted Execution Environment (TEE) provides a secure and isolated execution environment for sensitive applications. In order to design secure and trustworthy TEE-based systems, it is crucial to verify the trustworthiness of TEE implementations. Property checking is a promising avenue to guarantee that the TEE implementation satisfies the security properties. In the presence of a vulnerability, property checking will fail and provide a counterexample that can be utilized to fix the vulnerability. A major challenge in TEE property checking is that it relies on manual definition of the security properties, which can be cumbersome and error-prone. In this paper, we propose an efficient framework for automated generation and verification of TEE specific properties. Specifically, we leverage Finite State Machine (FSM) analysis to automatically derive and validate security properties utilizing templates. The effectiveness of the proposed method is demonstrated through experimental evaluation of Intel Trust Domain Extension (TDX), highlighting its potential for verifying security and trustworthiness of modern trusted execution environments.

关键词： Concurrent computing Memory management europe Automata Manuals Safety Security

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