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Security Assertions for Trusted Execution Environments

Security Assertions for Trusted Execution Environments

引用

design, automation and test in europe conference and Exhibition

作者： Hasini Witharana Hansika Weerasena Prabhat Mishra Department of Computer & Information Science & Engineering University of Florida Gainesville Florida USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Trusted Execution Environment (TEE) provides a secure and isolated execution environment for sensitive applications. In order to design secure and trustworthy TEE-based systems, it is crucial to verify the trustworthiness of TEE implementations. Property checking is a promising avenue to guarantee that the TEE implementation satisfies the security properties. In the presence of a vulnerability, property checking will fail and provide a counterexample that can be utilized to fix the vulnerability. A major challenge in TEE property checking is that it relies on manual definition of the security properties, which can be cumbersome and error-prone. In this paper, we propose an efficient framework for automated generation and verification of TEE specific properties. Specifically, we leverage Finite State Machine (FSM) analysis to automatically derive and validate security properties utilizing templates. The effectiveness of the proposed method is demonstrated through experimental evaluation of Intel Trust Domain Extension (TDX), highlighting its potential for verifying security and trustworthiness of modern trusted execution environments.

关键词： Concurrent computing Memory management europe Automata Manuals Safety Security

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Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems

Criticality and Requirement Aware Heterogeneous Coherence fo...

引用

design, automation and test in europe conference and Exhibition

作者： Safin Bayes Mohamed Hassan McMaster University Canada

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

We propose $\mathsf{CoHoRT}$ , as the first heterogeneous cache coherent solution for mixed criticality systems (MCS) equipped with several features that targets the characteristics and requirements of such systems. $\mathsf{CoHoRT}$ is requirement-aware. It provides an optimization engine to optimally configure the architecture based on system requirements. $\mathsf{CoHoRT}$ is also criticality-aware. It introduces a low-cost novel architecture to enable cores to heterogeneously run different coherence protocols (time-based and MSI-based protocols). Moreover, it enables a run-time switch between these protocols to provide hardware support for mode operation switch, which is a common chal-lenge in MCS. Our evaluation shows that $\mathsf{CoHoRT}$ outperforms existing solutions both from worst-case memory latency as well as overall average performance. It also illustrates that $\mathsf{CoHoRT}$ is able to meet timing requirements in various MCS setups and showcases $\mathsf{CoHoRT}$ 's ability to adapt to mode switches.

关键词： Protocols Memory management europe Switches Coherence Hardware Timing Registers Optimization Engines

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Late Breaking Results: Automatic Anomaly Detection Method in Physical Unclonable Functions using Data Mining Techniques

Late Breaking Results: Automatic Anomaly Detection Method in...

引用

design, automation and test in europe conference and Exhibition

作者： Mohammad Reza Heidari Iman Sergio Vinagrero Gutierrez Elena-Ioana Vatajelu Giorgio Di Natale Univ. Grenoble Alpes CNRS Grenoble INP* TIMA Grenoble France Institut des Nanotechnologies de Lyon (INL)

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Physical Unclonable Functions (PUFs) present a promising alternative to traditional cryptographic techniques for securing sensitive information in modern circuits. By exploiting inherent process variability, PUFs generate unique secrets dynamically, thus eliminating the need for data storage. However, a major challenge in PUF-based security is distinguishing valid PUFs from those that may have been tampered with or are invalid (i.e., not belonging to the original design). This paper proposes a data mining-based approach for detecting anomalies and identifying tampered or invalid PUFs. The proposed method mines a set of rules that describe the expected behavior of the PUF, with deviations from these rules signaling potential security issues and vulnerabilities. Experimental results demonstrate that the method effectively identifies invalid or tampered PUFs, showcasing its potential for enhancing PUF-based security systems.

关键词： Circuits Memory europe Physical unclonable function Cryptography Anomaly detection

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ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs

ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs

引用

design, automation and test in europe conference and Exhibition

作者： Afolabi Ige Jennifer Hasler School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Synthesis tools can unlock the potential of analog architectures to achieve real-time computation, signal processing, inference and learning for low $S$ WaP systems in commercial timescales. We present a methodology and results towards system analog and mixed-signal synthesis both for FPAAs and Custom Analog IC design. Building on previously efforts on large-scale Field Programmable Analog Arrays (FPAA) targeting tools enables tools capable of synthesizing new ICs. The IC synthesis is built upon our recent work on analog & mixed-signal programmable CMOS standard cell library that can be used across a range of CMOS process nodes (e.g. 180nm, 130nm, 65nm, 28nm, and 16nm CMOS). The entire tool-flow is being developed as an open-source tool that can be widely available. These approaches enable moving analog and mixed-signal design towards structured design Space Exploration (DSE).

关键词： Microprocessors Buildings europe Field programmable analog arrays Computer architecture CMOS process Real-time systems Libraries Space exploration Standards

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A System Level Performance Evaluation for Superconducting Digital Systems

A System Level Performance Evaluation for Superconducting Di...

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design, automation and test in europe conference and Exhibition

作者： Joyjit Kundu Debjyoti Bhattacharjee Nathan Josephsen Ankit Pokhrel Udara De Silva Wenzhe Guo Steven Van Winckel Steven Brebels Quentin Herr Anna Herr Manu Perumkunnil imec Leuven Belgium imec Florida USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Superconducting Digital (SCD) technology offers significant potential for enhancing the performance of next generation large scale compute workloads. By leveraging advanced lithography and a 300 mm platform, SCD devices can reduce energy consumption and boost computational power. This paper presents a cross-layer modeling approach to evaluate the system-level performance benefits of SCD architectures for Large Language Model (LLM) training and inference. Our findings, based on experimental data and Pulse Conserving Logic (PCL) design principles, demonstrate substantial performance gain in both training and inference. We are, thus, able to convincingly show that the SCD technology can address memory and interconnect limitations of present day solutions for next-generation compute systems.

关键词： Performance evaluation Training Energy consumption Superconducting logic circuits Large language models Lithography europe Performance gain Logic Next generation networking

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RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing Elements

RoTA: Rotational Torus Accelerator for Wear Leveling of Neur...

引用

design, automation and test in europe conference and Exhibition

作者： Taesoo Lim Hyeonjin Kim Jingu Park Bogil Kim William J. Song School of Electrical and Electronic Engineering Yonsei University Seoul South Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper introduces a reliability-aware neural accelerator design with a wear-leveling solution that balances the utilization of processing elements (PEs). Neural accelerators deploy many PEs to exploit data-level parallelism, but their designs and operations have focused mostly on performance and energy efficiency metrics. Directional dataflows in PE arrays and dimensional misalignment with variable-sized neural layers cause the underutilization of PEs, which is biased to PE locations and gradually accumulated over time. Consequently, the accelerators experience severe usage imbalance between PEs. To resolve the problem, this paper proposes a rotational torus accelerator (RoTA) with an optimized wear-leveling scheme that shuffles PE utilization spaces to eliminate PE usage imbalance. Evaluation results show that RoTA improves lifetime reliability by 1.69x.

关键词： Measurement Degradation Energy resolution europe Parallel processing Reliability engineering Energy efficiency

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Image Computation for Quantum Transition Systems

Image Computation for Quantum Transition Systems

引用

design, automation and test in europe conference and Exhibition

作者： Xin Hong Dingchao Gao Sanjiang Li Shenggang Ying Mingsheng Ying Key Laboratory of System Software (Chinese Academy of Sciences) and State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijing China Centre for Quantum Software and Information University of Technology Sydney Sydney Australia

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

With the rapid progress in quantum hardware and software, the need for verification of quantum systems becomes increasingly crucial. While model checking is a dominant and very successful technique for verifying classical systems, its application to quantum systems is still an underdeveloped research area. This paper advances the development of model checking quantum systems by providing efficient image computation algorithms for quantum transition systems, which play a fundamental role in model checking. In our approach, we represent quantum circuits as tensor networks and design algorithms by leveraging the properties of tensor networks and tensor decision diagrams. Our experiments demonstrate that our contraction partition-based algorithm can greatly improve the efficiency of image computation for quantum transition systems.

关键词： Quantum system Tensors europe Model checking Software Hardware Partitioning algorithms Computational efficiency Quantum circuit

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Algorithm-Hardware Co-design of a Unified Accelerator for Non-Linear Functions in Transformers

Algorithm-Hardware Co-Design of a Unified Accelerator for No...

引用

design, automation and test in europe conference and Exhibition

作者： Haonan Du Chenyi Wen Zhengrui Chen Li Zhang Qi Sun Zheyu Yan Cheng Zhuo Zhejiang University Hubei University Of Technology

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Nonlinear functions (NFs) in Transformers require high-precision computation consuming significant time and energy, despite the aggressive quantization schemes for other components. Piece-wise Linear (PWL) approximation-based methods offer more efficient processing schemes for NFs but fall short in dealing with functions with high nonlinearities. Moreover, PWL-based methods still suffer from inevitably high latency introduced by the Multiply-And-Add (MADD) unit. To address these issues, this paper proposes a novel quadratic approximation scheme and a highly integrated, multiplier-less hardware structure, as a unified method to accelerate any unary nonlinear function. We also demonstrate implementation examples for GELU, Softmax, and LayerNorm. The experimental results show that the proposed method achieves up to 5.41% higher inference accuracy and 60.12% lower area-delay product.

关键词： Accuracy Quantization (signal) Computational modeling europe Life estimation Transformers Approximation algorithms Hardware Inference algorithms Integrated circuit modeling

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HAAN: A Holistic Approach for Accelerating Normalization Operations in Large Language Models

HAAN: A Holistic Approach for Accelerating Normalization Ope...

引用

design, automation and test in europe conference and Exhibition

作者： Tianfan Peng Tianhua Xia Jiajun Qin Sai Qian Zhang Tandon School of Engineering New York University New York USA Shenzhen Institute of Information Technology Shenzhen China Zhejiang University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Large language models (LLMs) have revolutionized natural language processing (NLP) tasks by achieving state-of-the-art performance across a range of benchmarks. Central to the success of these models is the integration of sophisticated architectural components aimed at improving training stability, convergence speed, and generalization capabilities. Among these components, normalization operation, such as layer normalization (LayerNorm), emerges as a pivotal technique, offering substantial benefits to the overall model performance. However, previous studies have indicated that normalization operations can substantially elevate processing latency and energy usage. In this work, we adopt the principles of algorithm and hardware co-design, introducing a holistic normalization accelerating method named HAAN. The evaluation results demonstrate that HAAN can achieve significantly better hardware performance compared to state-of-the-art solutions.

关键词： Training Correlation Large language models europe Benchmark testing Natural language processing Hardware Stability analysis Convergence

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New Challenges in the Implementation and Exploitation of a Low-Cost Web Map of the Active Deformation Areas Across europe 9

New Challenges in the Implementation and Exploitation of a L...

引用

9th International conference on Geographical Information Systems Theory, Applications and Management, GISTAM 2023

作者： Navarro, José A. García, Danielly Crosetto, Michele Av. Carl Friedrich Gauss 7 Castelldefels08860 Spain

ISBN: (纸本)9789897586491

The european Ground Motion Service (EGMS) is already offering data on Persistent Scatterers (PS) throughout europe, which will aid in analyzing ground deformation on a continental scale. However, to more fully comprehend ground motion processes, it is preferable to use Active Deformation Areas (ADA) instead of PS. The CTTC has been using its ADAfinder tool to generate ADAs since 2018. With the new availability of EGMS PS data for the entire continent, the CTTC is now working on producing ADAs for all of europe and making them accessible to the public through a self-developed, in-house hosted, web-based map application. A former paper describes the initial steps taken to develop it. This work focuses on how the challenge of processing a huge amount of data has affected the design and implementation of the tools used in the data production workflow. Additionally, the manner in which the EGMS data is structured, providing data sets that spatially overlap, has resulted in a new problem: overlapping ADAs. The approach to resolving this issue is also discussed in this paper. The result is an evolution of the initial concept where not only economic reasons but also considerations on automation and handling of large volumes of data have guided the design and implementation of the system. Copyright © 2023 by SCITEPRESS – Science and Technology Publications, Lda.

关键词： Costs

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