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Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based test Generation

Comprehensive RISC- V Floating-Point Verification: Efficient...

引用

design, automation and test in europe conference and Exhibition

作者： Tianyao Lu Anlin Liu Bingjie Xia Peng Liu College of Information Science and Electronic Engineering Zhejiang University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The increasing complexity of processor architectures necessitates more rigorous functional verification. Floating-point operations, in particular, present significant challenges due to their extensive range of computational cases that require verification. This paper proposes a comprehensive approach for generating floating-point instruction sequences to enhance the verification of RISC-V. We introduce a constraint-based method for floating-point test generation and design efficient coverage models as input constraints for this process. The resulting representative floating-point tests are integrated with RISC-V instruction sequence generation through a memory-bound register update method. Experimental results demonstrate that our approach improves the functional coverage of RISC-V floating-point instruction sequences from 93.32% to 98.34%, while simultaneously reducing the number of required instructions by 66.67% compared to the Google RISCV-DV generator. Additionally, our method achieves more comprehensive coverage of floating-point types in instruction write-back data compared to RISCV-DV. Using the proposed approach, we successfully detect representative floating-point-related faults injected into the RISC-V processor CV32E40P, thereby demonstrating its effectiveness.

关键词： Computational modeling Diversity reception Computer bugs europe Computer architecture Generators Registers Internet test pattern generators Reliability

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SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis

SynDCIM: A Performance-Aware Digital Computing-in-Memory Com...

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design, automation and test in europe conference and Exhibition

作者： Kunming Shao Fengshi Tian Xiaomeng Wang Jiakun Zheng Jia Chen Jingyu He Hui Wu Jinbo Chen Xihao Guan Yi Deng Fengbin Tu Jie Yang Mohamad Sawan Tim Kwang-Ting Cheng Chi-Ying Tsui The Hong Kong University of Science and Technology Hong Kong SAR China AI Chip Center for Emerging Smart Systems (ACCESS) Hong Kong SAR China Westlake University Hangzhou China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable the agile design of DCIM macros with optimal architectures, we present SynDCIM - a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.

关键词： Limiting design automation europe Manuals Computer architecture Libraries Logic Artificial intelligence Logic arrays testing

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design OF VIBRATION test FIXTURE FOR SOME SPACECRAFT 9

DESIGN OF VIBRATION TEST FIXTURE FOR SOME SPACECRAFT

引用

9th International Symposium on test automation and Instrumentation, ISTAI 2022

作者： Lin, Cheng Gen, Yang S. Engineering Systems Research Department The 38th Research Institute of CETC Hefei China

ISBN: (纸本)9781839538391

Vibration test is an effective means to test the resistance environment of aerospace equipment. The performance of vibration fixture determines the effectiveness of vibration test. The basic requirements of the vibration test fixture are as follows: *** frequency response characteristic of the vibration fixture is flat, and the first natural frequency is 3-5 times greater than the frequency response of the specimen. 2. The structural damping of the vibration fixture should be large, and the number of the bolt connections can be appropriately increased, or the rubber pad is laid on the vibration table. 3. The orthogonal corresponding of vibration fixture should be small, cantilever structure design should be avoid. © 2022 IET conference proceedings. All rights reserved.

关键词： Frequency response

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HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

HaVen: Hallucination-Mitigated LLM for Verilog Code Generati...

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design, automation and test in europe conference and Exhibition

作者： Yiyao Yang Fu Teng Pengju Liu Mengnan Qi Chenyang Lv Ji Li Xuhong Zhang Zhezhi He School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China School of Software Technology Zhejiang University Ningbo China Independent Researcher

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a gap between the ability of LLMs and the practical demands of hardware description language (HDL) engineering. This gap includes differences in how engineers phrase questions and hallucinations in the code generated. To address these chal-lenges, we introduce Haven, a novel LLM framework designed to mitigate hallucinations and align Verilog code generation with the practices of HDL engineers. Haven tackles hallucination issues by proposing a comprehensive taxonomy and employing a chain-of-thought (CoT) mechanism to translate symbolic modalities (e.g. truth tables, state diagrams, etc.) into accurate natural language descriptions. Furthermore, Haven bridges this gap by using a data augmentation strategy. It synthesizes high-quality instruction-code pairs that match real HDL engineering practices. Our experiments demonstrate that Haven significantly improves the correctness of Verilog code generation, outperforming state-of-the-art LLM-based Verilog generation methods on VerilogEval and RTLLM benchmark. Haven is publicly available at https://***/Intelli2ent-Computing-Research-Group/HaVen.

关键词： Bridges Codes Translation design automation Large language models Taxonomy europe Data augmentation Hardware Hardware design languages

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design and test of Precision Seeding System Based on Fuzzy PID

Design and Test of Precision Seeding System Based on Fuzzy P...

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2023 International conference on automation Control, Algorithm, and Intelligent Bionics, ACAIB 2023

作者： Hou, Yuntao Wu, Zequan Cai, Xiaohua Li, Zhancheng Heilongjiang Academy of Agricultural Machinery Sciences Heilongjiang Academy of Agriculture Sciences Heilongjiang Harbin150081 China

ISBN: (纸本)9781510667662

To achieve precise seeding operations, an electric control precise seeding system was designed in this paper, in which a brushless DC motor was used to provide power for the seeding device. A double-closed-loop control model of the brushless DC motor was established and simulated, and a seeding device test bench experiment was conducted. The simulation results showed that the system had fast response, no overshoot, and good dynamic and static performance. The seeding device test bench experiment showed that the qualified seeding index was greater than 96.64%, the missing seeding index was less than 1.34%, the redundant seeding index was less than 2.01%, and the variation coefficient was less than 17.61%. The seeding uniformity was good, and the difference in seeding quality index was within 5%, which met the requirements of the JB/T 10293-2013 "Technical Conditions of Single-Grain (Precision) Seeder". The seeding stability was also good. © 2023 SPIE.

关键词： Brushless DC motors

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design of Android remote monitoring system for multi-channel fatigue test bench 34

Design of Android remote monitoring system for multi-channel...

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34th Chinese Control and Decision conference, CCDC 2022

作者： Qi, Haoquan Zhao, Jianyu Wang, Xudong University of Jinan School of Automation and Electrical Engineering Jinan250002 China Jinan DOCER Testing Machine Technology Co. Ltd Jinan250002 China

ISBN: (纸本)9781665478960

As a comprehensive fatigue life testing equipment in the testing machine industry, the multi-channel fatigue test bench is mainly used for the durability test of various types of complete machines and components. Due to the long duration of the fatigue test and various unexpected conditions accompanying the test, the monitoring task of test is heavy. In view of this situation, this paper designs an Android-based IoT remote monitoring system with the multi-channel fatigue test bench as the monitoring object, and develops the client monitoring software RMCmp under the Android system. Adopting TCP protocol of Socket mechanism and using cloud server as communication relay, the mobile remote monitoring of fatigue test bench by Android client is realized. After the completion of the design, functional trials were conducted on the system, and the trials results showed that the system performed stably and well and achieved the expected results. © 2022 IEEE.

关键词： Fatigue testing

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Exact Schedulability Analysis for Limited-Preemptive Parallel Applications Using Timed Automata in UPPAAL

Exact Schedulability Analysis for Limited-Preemptive Paralle...

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design, automation and test in europe conference and Exhibition

作者： Jonas Hansen Srinidhi Srinivasan Geoffrey Nelissen Kim G. Larsen DEIS Aalborg Universitet Aalborg Denmark IRIS Eindhoven University of Technology Eindhoven The Netherlands

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

We study the problem of verifying schedulability and ascertaining response time bounds of limited-preemptive parallel applications with uncertainty, scheduled on multi-core platforms. While sufficient techniques exist for analysing schedulability and response time of parallel applications under fixed-priority scheduling, their accuracy remains uncertain due to the lack of a scalable and exact analysis that can serve as a ground-truth to measure the pessimism of existing sufficient analyses. In this paper, we address this gap using formal methods. We use Timed Automata and the powerful UPPAAL verification engine to develop a generic approach to model parallel applications and provide a scalable and exact schedulability and response time analysis. This work establishes a benchmark for evaluating the accuracy of both existing and future sufficient analysis techniques. Furthermore, our solution is easily extendable to more complex task models thanks to its flexible model architecture.

关键词： Adaptation models Accuracy Uncertainty Measurement uncertainty Automata europe Benchmark testing Parallel processing Time measurement Time factors

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SMT-Based Repairing Real-Time Task Specifications

SMT-Based Repairing Real-Time Task Specifications

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design, automation and test in europe conference and Exhibition

作者： Anand Yeolekar Ravindra Metta Samarjit Chakraborty TCS Research India TUM Germany Dept. of CS UNC Chapel Hill USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

When addressing timing issues in real-time systems, approaches for systematic timing debugging and repair have been missing due to (i) Lack of available feedback: most timing analysis techniques, being closed-form analytical techniques, are unable to provide root cause information when a timing property is violated, which is critical for identifying an appropriate repair, and (ii) Pessimism in the analysis: existing schedulability analysis techniques tend to make worst case assumptions in the presence of non-determinism introduced by real-world factors such as release jitter, or sporadic tasks. To address this gap, we propose an SMT encoding of task runs for exact debugging of timing violations, and a procedure to iteratively repair a given task specification. We demonstrate the utility of this procedure by repairing example task sets scheduled under global non-preemptive earliest-deadline-first scheduling, a common choice for many safety-critical systems.

关键词： Systematics europe Debugging Maintenance engineering Jitter Real-time systems Encoding Timing

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Enabling Security on the Edge: A CHERI Compartmentalized Network Stack

Enabling Security on the Edge: A CHERI Compartmentalized Net...

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design, automation and test in europe conference and Exhibition

作者： Donato Ferraro Andrea Bastoni Alexander Zuepke Andrea Marongiu University of Modena and Reggio Emilia Minerva Systems Technical University of Munich

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The widespread deployment of embedded systems in critical infrastructures, interconnected edge devices like autonomous drones, and smart industrial systems requires robust security measures. Compromised systems increase the risks of operational failures, data breaches, and-in safety-critical environments-potential physical harm to people. Despite these risks, current security measures are often insufficient to fully address the attack surfaces of embedded devices. CHERI provides strong security from the hardware level by enabling fine-grained compartmentalization and memory protection, which can reduce the attack surface and improve the reliability of such devices. In this work, we explore the potential of CHERI to compartmentalize one of the most critical and targeted components of interconnected systems: their network stack. Our case study examines the tradeoffs of isolating applications, TCP/IP libraries, and network drivers on a CheriBSD system deployed on the Arm Morello platform. Our results suggest that CHERI has the potential to enhance security while maintaining performance in embedded-like environments.

关键词： Embedded systems Current measurement europe TCPIP Interconnected systems Libraries Hardware Security Reliability Protection

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HiDP:Hierarchical DNN Partitioning for Distributed Inference on Heterogeneous Edge Platforms

HiDP:Hierarchical DNN Partitioning for Distributed Inference...

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design, automation and test in europe conference and Exhibition

作者： Zain Taufique Aman Vyas Antonio Miele Pasi Liljeberg Anil Kanduri University of Turku Turku Finland Politecnico di Milano Milan Italy

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Edge inference techniques partition and distribute Deep Neural Network (DNN) inference tasks among multiple edge nodes for low latency inference, without considering the core-level heterogeneity of edge nodes. Further, default DNN inference frameworks also do not fully utilize the resources of heterogeneous edge nodes, resulting in higher inference latency. In this work, we propose a hierarchical DNN partitioning strategy (HiDP) for distributed inference on heterogeneous edge nodes. Our strategy hierarchically partitions DNN workloads at both global and local levels by considering the core-level heterogeneity of edge nodes. We evaluated our proposed HiDP strategy against relevant distributed inference techniques over widely used DNN models on commercial edge devices. On average our strategy achieved 38% lower latency, 46% lower energy, and 56% higher throughput in comparison with other relevant approaches,

关键词： europe Artificial neural networks Edge AI Throughput Low latency communication

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