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A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscillators

A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscil...

引用

design, automation and test in europe conference and Exhibition

作者： Yilmaz Ege Gonul Baris Taskin Drexel University Philadelphia PA USA

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This work presents a multi-stage coupled ring oscillator based Potts machine, designed with phase-shifted Sub-Harmonic-Injection-Locking (SHIL) to represent multivalued Potts spins at different solution stages with oscillator phases. The proposed Potts machine is able to solve a certain class of combinatorial optimization problems that natively require multivalued spins with a divide-and-conquer approach, facilitated through the alternating phase-shifted SHILs acting on the oscillators. The proposed architecture eliminates the need for any external intermediary mappings or usage of external memory, as the influence of SHIL allows oscillators to act as both memory and computation units. Planar 4-coloring problems of sizes up to 2116 nodes are mapped to the proposed architecture. Simulations demonstrate that the proposed Potts machine provides exact solutions for smaller problems (e.g. 49 nodes) and generates solutions reaching up to 97% accuracy for larger problems (e.g. 2116 nodes).

关键词： Ring oscillators Semiconductor device modeling Accuracy Costs Computational modeling europe Computer architecture Optimization

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Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis

Clock and Power Supply-Aware High Accuracy Phase Interpolato...

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design, automation and test in europe conference and Exhibition

作者： Siou-Sian Lin Shih-Yu Chen Yu-Ping Huang Tzu-Chuan Lin Hung-Ming Chen Wei-Zen Chen Inst. of Electronics National Yang Ming Chiao Tung University Hsinchu City Taiwan

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Due to popular requests from the designers of clock and data recovery (CDR) regarding the inefficiency of generating high accuracy phase interpolator (PI), in this work, we have developed a layout generator for such circuit, different from conventional constraint-driven works. In the first stage, we propose a customized template floorplanning plus pin generation demanded by the users. In the second stage, in order to generate high accuracy layout, we implement a gridless router for signal, power supply and clock. Experiments with several configurations indicate that our approach can generate high-quality corresponding layouts that align with user expectations, and even surpass the quality of manual designs on structurally regular high-performance PIs, which are not easy and efficient to be generated by prior primitive/grid-based methods.

关键词： Accuracy Power supplies Layout europe Manuals Analog circuits Routing Generators Pins Clocks

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Analog Circuit Anti-Piracy Security by Exploiting Device Ratings

Analog Circuit Anti-Piracy Security by Exploiting Device Rat...

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design, automation and test in europe conference and Exhibition

作者： Hazem H. Hammam Hassan Aboushady Haralampos-G. Stratigopoulos CNRS LIP6 Sorbonne Université Paris France

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

We propose a novel anti-piracy security technique for analog and mixed-signal (AMS) circuits. The circuit is re-designed by obfuscating transistors and capacitors with key-controlled versions. We obfuscate both the device geometries and their ratings, which define the maximum allowable current, voltage, and power dissipation. The circuit is designed to function correctly only with a specific key. Loading any other incorrect key degrades performance and for the vast majority of these keys the chip is damaged because of electrical over-stress. This prevents counter-attacks that employ a chip to search for the correct key. The methodology is demonstrated on a low-dropout regulator (LDO) designed in the 22nm FDSOI technology by GlobalFoundries. By locking the LDO, the entire chip functionality breaks unless the LDO is unlocked first. The secured LDO shows no performance penalty and area overhead is justifiable and less than 25%, while it is protected against all known counter-attacks in the AMS domain.

关键词： Performance evaluation Geometry Regulators Hardware security Loading Capacitors Silicon-on-insulator europe Power dissipation Transistors

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Genetic Algorithm Based EFSM Regression test Sequence Generation 23

Genetic Algorithm Based EFSM Regression Test Sequence Genera...

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23rd IEEE International conference on Software Quality, Reliability, and Security Companion, QRS-C 2023

作者： Li, Jiahao Yang, Chengru Wang, Yichen School of Reliability and Systems Engineering Beihang University Beijing China

ISBN: (纸本)9798350359398

Regression testing is part of every testing phase in software testing and plays a key role in software quality assurance. With the increasing complexity of software systems, it is often necessary to design test cases for regression testing to balance test adequacy and test overhead. Some studies have proposed algorithms for sequence completion, which generates only one test sequence to be completed at a time, generating test sequences with excessive overheads, and the method relies on a large amount of data flow information, and the degree of automation is also not high. To this end, this paper proposes a coverage criterion based on 'test obligation', which integrates the control flow and data flow information of the EFSM model as the coverage basis, and is used to guide the test sequence generation work to better reflect the dependency relationships on the EFSM, and accurately determine the range of the regression test. Based on the proposed test obligation coverage criterion, a genetic algorithm for regression testing test sequence generation is designed and implemented by combining test obligation coverage diversity and test sequence length as a fitness function. Experiments show that the test sequence set generated by this algorithm is better than the existing methods in terms of test sequence length and number of test sequences, which effectively reduces the regression test overhead and improves the test sequence generation efficiency. © 2023 IEEE.

关键词： Software testing

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High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms

High-Performance ARM-on-ARM Virtualization for Multicore Sys...

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design, automation and test in europe conference and Exhibition

作者： Nils Bosbach Rebecca Pelke Niko Zurstraßen Jan Henrik Weinstock Lukas Jünger Rainer Leupers RWTH Aachen University Aachen Germany MachineWare GmbH Aachen Germany

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The increasing complexity of hardware and software requires advanced development and test methodologies for modern systems on chips. This paper presents a novel approach to ARM-on-ARM virtualization within SystemC-based simulators using Linux's KVM to achieve high-performance simulation. By running target software natively on ARM-based hosts with hardware-based virtualization extensions, our method eliminates the need for instruction-set simulators, which significantly improves performance. We present a multicore SystemC-TLM-based CPU model that can be used as a drop-in replacement for an instruction-set simulator. It places no special requirements on the host system, making it compatible with various environments. Benchmark results show that our ARM-on-ARM-based virtual platform achieves up to 10 x speedup over traditional instruction-set-simulator-based models on compute-intensive workloads. Depending on the benchmark, speedups increase to more than 100 x.

关键词： Multicore processing Computational modeling Linux europe Benchmark testing Software Hardware System-on-chip Complexity theory Virtualization

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Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking

Using OFF-set only for Corrupting Circuit to Resist Structur...

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design, automation and test in europe conference and Exhibition

作者： Hsiang-Chun Cheng RuiJie Wang TingTing Hwang Department of Computer Science National Tsing Hua University Hsinchu Taiwan

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Corrupt-and-Correct (CAC) Logic Lockings [1]–[4] are state-of-the-art hardware security techniques designed to protect IC/IP designs from IP piracy, reverse engineering, overproduction, and unauthorized use. Although these techniques are resilient to SAT-based attacks, they remain vulnerable to structural attacks, which exploit structural traces left by the synthesis tool to recover the original form. In this paper, we will propose a novel method that uses only the OFF-set to corrupt the circuit. This approach helps the added circuitry better merge with the original circuit, thereby thwarting structural attacks while maintaining resilience to SAT-based attacks. Additionally, we demonstrate that our proposed method can incur less area overhead compared to previous locking methods in HIID [5]. Compared to SFLL-rem [4], our method can achieve comparable area overhead while effectively resisting structural attacks, including Valkyrie [6] and SPI attacks [7].

关键词： Hardware security Reverse engineering europe Resists Logic IP networks Protection Resilience

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SparseInfer: Training-free Prediction of Activation Sparsity for Fast LLM Inference

SparseInfer: Training-free Prediction of Activation Sparsity...

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design, automation and test in europe conference and Exhibition

作者： Jiho Shin Hoeseok Yang Youngmin Yi University of Seoul Seoul South Korea Santa Clara University Santa Clara CA USA Sogang University Seoul South Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Leveraging sparsity is crucial for optimizing large language model (LLM) inference; however, modern LLMs employing SiLU as their activation function exhibit minimal activation sparsity. Recent research has proposed replacing SiLU with ReLU to induce significant activation sparsity and showed no downstream task accuracy degradation through fine-tuning. However, taking full advantage of it required training a predictor to estimate this sparsity. In this paper, we introduce Sparselnfer, a simple, lightweight, and training-free predictor for activation sparsity of ReLU-fied LLMs, in which activation sparsity is predicted by comparing only the sign bits of inputs and weights. To compensate for possible prediction inaccuracy, an adaptive tuning of the predictor's conservativeness is enabled, which can also serve as a control knob for optimizing LLM inference. The proposed method achieves approximately 21% faster inference speed over the state-of-the-art, with negligible accuracy loss of within 1 % p.

关键词： Training Degradation Accuracy Large language models Memory management europe Predictive models Vectors Computational efficiency Tuning

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A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory

A Low-Complexity True Random Number Generation Scheme Using ...

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design, automation and test in europe conference and Exhibition

作者： Ruibin Zhou Jian Huang Xianping Liu Yuhan Wang Xinrui Zhang Yungen Peng Zhiyi Yu School of Microelectronics Science and Technology Sun Yat-sen University Zhuhai China Peng Cheng Laboratory Shenzhen China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Unpredictable true random numbers are essential in cryptographic applications and secure communications. However, implementing True Random Number Generators (TRNGs) typically requires specialized hardware devices. In this paper, we propose a low-complexity true random number extraction scheme that can be implemented in endpoint systems containing 3D-NAND flash memory chips, addressing the need for random numbers without requiring additional complex hardware. We successfully utilized the randomness of the rapid charging and discharging of shallow charge traps in 3D-NAND memory as an entropy source. The proposed approach only requires conventional user-mode erase, program, and read operations, without any special timing control. We successfully extracted random bitstream using this scheme without a post-debiasing process. We evaluated the randomness of the generated bitstream using the NIST SP 800–22 statistical test suite, and it passed all 15 tests.

关键词： europe NIST Hardware Generators Entropy Timing Flash memories Random number generation Binary sequences

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RTHeter: Simulating Real-Time Scheduling of Multiple Tasks on Heterogeneous Architectures

RTHeter: Simulating Real-Time Scheduling of Multiple Tasks o...

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design, automation and test in europe conference and Exhibition

作者： Yinchen Ni Jiace Zhu Yier Jin An Zou Shanghai Jiao Tong University University of Florida

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The rising popularity of AI applications is driving the adoption of heterogeneous computing architectures to handle complex computations. However, as these heterogeneous architectures grow more complex, optimizing the scheduling of multiple tasks and meeting strict timing constraints becomes significantly challenging. Current studies on real-time scheduling on heterogeneous processors lack agile and flexible simulation tools that can quickly adapt to varying system settings, leading to inefficiencies in system design. Additionally, the high costs associated with evaluating real-time performance in terms of human and facility efforts further complicate the development process. To address these challenges, this paper introduces a comprehensive hierarchical simulating approach and a corresponding simulator designed for flexible heterogeneous computing platforms. The simulator supports ideal or practical, off-the-shelf or customizable heterogeneous architectures, upon which the simulator can execute both parallel and dependent tasks. Utilizing this simulator, we present two case studies that were time-consuming previously but are now easily achieved by the proposed simulator. The first case study reveals the possibility of using policy-based reinforcement learning to explore novel scheduling strategies; the second explores the dominant processors within heterogeneous architectures, providing insights for optimizing the heterogeneous architecture design.

关键词： Program processors Costs Processor scheduling europe Computer architecture Reinforcement learning Real-time systems Heterogeneous networks Timing System analysis and design

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LowGradQ: Adaptive Gradient Quantization for Low-Bit CNN Training via Kernel Density Estimation-Guided Thresholding and Hardware-Efficient Stochastic Rounding Unit

LowGradQ: Adaptive Gradient Quantization for Low-Bit CNN Tra...

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design, automation and test in europe conference and Exhibition

作者： Sangbeom Jeong Seungil Lee Hyun Kim Department of Electrical and Information Engineering Research Center for Electrical and Information Technology Seoul National University of Science and Technology Seoul Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

This paper proposes a hardware-efficient INT8 training framework with dual-scale adaptive gradient quantization (DAGQ) to cope with the growing need for efficient on-device CNN training. DAGQ captures both small- and large-magnitude gradients, ensuring robust low-bit training with minimal quantization error. Additionally, to reduce the computational and memory demands of stochastic rounding in low-bit training, we introduce a reusable LFSR-based stochastic rounding unit (RLSRU), which efficiently generates and reuses random numbers, minimizing hardware complexity. The proposed framework achieves stable INT8 training across various networks with minimal accuracy loss while being implementable on RTL-based hardware accelerators, making it well-suited for resource-constrained environments.

关键词： Training Quantization (signal) Accuracy Memory management europe Computational efficiency Complexity theory Kernel Hardware acceleration

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