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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Zhou, Shengjie Chen, Yongliang Cui, Xiaole Liu, Yun Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen 518055 Peoples R China Peng Cheng Lab Shenzhen 518066 Peoples R China

ISBN: (纸本)9798350348606;9783981926385

Physical unclonable function (PUF) is widely used as the root of trust in the IoT systems. The sub-threshold voltage divider array PUF was reported as an anti-modeling-attack PUF. It utilizes the nonlinear I-V relationship in the subthreshold region of MOS transistors to improve the security. However, the security of this PUF has not been soundly analyzed. This work presents the simulation results of modeling attack tests which reveal the vulnerability of this PUF. In the attack, the sub-threshold voltage divider array PUF is modeled by a dedicated artificial neural network (ANN). The nonlinearity of the PUF is simplified based on its working principle. The simulation results show that the prediction accuracy achieves 97% when the number of training CRPs is 350 for the single-stage PUF, and it achieves 90% when the number of training CRPs is 300 for the multi-stage PUF. Furthermore, this work improves the original structure of the sub-threshold voltage divider array PUF, to enhance its anti-modeling-attack capability. The simulation results of modeling attack tests show that the prediction accuracy of the improved multi-stage PUF is reduced to about 50%, which implies that the improved PUF has a strong anti-modeling-attack capability.

关键词： The sub-threshold voltage divider array PUF modeling attack test ANN

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ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self test

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Par...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Zhang, Hongyi Zhu, Haozhe He, Siqi Li, Mengjie Wang, Chengchen Xiong, Xiankui Tian, Haidong Zeng, Xiaoyang Client, Chixiao Fudan Univ State Key Lab Integrated Chips & Syst Shanghai Peoples R China ZTE Corp State Key Lab Mobile Network & Mobile Multimedia Shenzhen Peoples R China

ISBN: (纸本)9798350348606;9783981926385

Digital Compute-in-Memory (DCIM) architectures are playing an increasingly vital role in artificial intelligence (AI) applications due to their significant energy efficiency enhancement. Coupling memory and computing logic in DCIM requires extensive customization of custom cells and layouts, thus increasing design complexity and implementation effort. To adapt to the swiftly evolving AI algorithms, DCIM compiler for agile customization is required. Previous DCIM compilers accelerate the customization process but only focus on integer computation. Moreover, with technology node scaling down, design-for-test circuits are critical for robust chip design, while previous built-in-self-test (BIST) schemes for traditional memory fail to offer support for DCIM. This paper presents ARCTIC, an agile and robust DCIM compiler supporting parameterized integer/floating-point formats with corresponding BIST circuits. To support variable precision formats (including integer and floating-point), ARCTIC applies adaptive topology and layout optimization schemes for optimal performance. The compiler is also equipped with DCIM-friendly MarchCIM BIST circuits for efficient post-silicon tests with negligible area overhead. The energy efficiency of the generated DCIM macros remains competent with the state-of-the-art counterparts.

关键词： Compute-in-memory Floating-point BIST Agile customization

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Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks

Frontiers in Edge AI with RISC-V: Hyperdimensional Computing...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Genssler, Paul R. Wasif, Sandy A. Wael, Miran Novkin, Rodion Amrouch, Hussam Univ Stuttgart Semicond Test & Reliabil Stuttgart Germany Tech Univ Munich Chair AI Processor Design Munich Germany TUM Sch Computat Informat & Technol Munich Germany Munich Inst Robot & Machine Intelligence Munich Germany

ISBN: (纸本)9798350348606;9783981926385

Hyperdimensional Computing (HDC) is an emerging paradigm that stands as a compelling alternative to conventional Deep Learning algorithms. HDC holds four key promises. First, the ability to learn from little data. Second, to be robust against noise in this data. HDC also promises to be resilient against errors in the underlying hardware. This includes the memory on which the model is stored and errors in the computations of the operations, which is attributed to the encoding of information across an expansive dimensional space. Fourth, HDC can be implemented efficiently in hardware due to its lightweight and embarrassingly parallel computations. In this work, those four key promises are evaluated in a holistic way. A fixed-point and a binary HDC implementation are compared against neural network implementations. The models are executed on a RISC-V processor to ensure a fair comparison. While the results confirm the ability to learn from little data and the resiliency against errors, the higher inference accuracy of neural networks favors them in most experiments. Based on these insights, we formulate challenges and opportunities for HDC. Our implementations for QNN, binary and fixed-point HDC are available online: https://***/TUM-AIPro/HDC-vs-QNN

关键词： Hyperdimensional computing Deep learning Machine Learning Edge AI RISC-V Reliability

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A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach

A System Development Kit for Big Data Applications on FPGA-b...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Pilato, Christian Banik, Subhadeep Beranek, Jakub Brocheton, Fabien Castrillon, Jeronimo Cevasco, Riccardo Cmar, Radim Curzel, Serena Ferrandi, Fabrizio Friebel, Karl F. A. Galizia, Antonella Grasso, Matteo Silva, Paulo Martinovic, Jan Palermo, Gianluca Paolino, Michele Parodi, Andrea Parodi, Antonio Pintus, Fabio Polig, Raphael Poulett, David Regazzoni, Francesco Ringlein, Burkhard Rocco, Roberto Slaninova, Katerina Slooff, Tom Soldavini, Stephanie Suchert, Felix Tibaldi, Mattia Weiss, Beat Hagleitner, Christoph IBM Res Europe Ruschlikon Switzerland Politecn Milan Milan Italy Univ Svizzera Italiana Lugano Switzerland Tech Univ Dresden Dresden Germany Ctr Int Monitoraggio Ambientale Savona Italy VSB Tech Univ Ostrava IT4Innovat Ostrava Czech Republic Virtual Open Syst Grenoble France Duferco Energia Genoa Italy NUMTECH Aubiere France Sygic Bratislava Slovakia CNR IMATI Rome Italy Univ Amsterdam Amsterdam Netherlands

ISBN: (纸本)9798350348606;9783981926385

Modern big data workflows are characterized by computationally intensive kernels. The simulated results are often combined with knowledge extracted from AI models to ultimately support decision-making. These energy-hungry workflows are increasingly executed in data centers with energy-efficient hardware accelerators since FPGAs are well-suited for this task due to their inherent parallelism. We present the H2020 project EVEREST, which has developed a system development kit (SDK) to simplify the creation of FPGA-accelerated kernels and manage the execution at runtime through a virtualization environment. This paper describes the main components of the EVEREST SDK and the benefits that can be achieved in our use cases.

关键词： Field programmable gate arrays (FPGA)

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Security layers and related services within the Horizon europe NEUROPULS project

Security layers and related services within the Horizon Euro...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Pavanello, Fabio Marchand, Cedric Jimenez, Paul Letartre, Xavier Chaves, Ricardo Marastoni, Niccolo Lovato, Alberto Ceccato, Mariano Papadimitriou, George Karakostas, Vasileios Gizopoulos, Dimitris Bardini, Roberta Carmona, Tzamn Melendez Di Carlo, Stefano Savino, Alessandro Lerch, Laurence Ruhrmair, Ulrich Gutierrez, Sergio Vinagrero Di Natale, Giorgio Vatajelu, Elena Ioana Univ Grenoble Alpes Univ Savoie Mt Blanc CROMA Grenoble INPCNRS Grenoble France Univ Claude Bernard Lyon 1 Univ Lyon Ecole Cent Lyon CNRSINLINSA LyonCPE Lyon Ecully France ULisboa IST INESC ID Lisbon Portugal Univ Verona Dept Comp Sci Verona Italy Natl & Kapodistrian Univ Athens Dept Informat & Telecommun Athens Greece Politecn Torino Control & Comp Engn Dept Turin Italy Tech Univ Berlin Berlin Germany Univ Grenoble Alpes TIMA Grenoble INP CNRS F-38000 Grenoble France

ISBN: (纸本)9798350348606;9783981926385

In the contemporary security landscape, the incorporation of photonics has emerged as a transformative force, unlocking a spectrum of possibilities to enhance the resilience and effectiveness of security primitives. This integration represents more than a mere technological augmentation;it signifies a paradigm shift towards innovative approaches capable of delivering security primitives with key properties for low-power systems. This not only augments the robustness of security frameworks, but also paves the way for novel strategies that adapt to the evolving challenges of the digital age. This paper discusses the security layers and related services that will be developed, modeled, and evaluated within the Horizon europe NEUROPULS project. These layers will exploit novel implementations for security primitives based on physical unclonable functions (PUFs) using integrated photonics technology. Their objective is to provide a series of services to support the secure operation of a neuromorphic photonic accelerator for edge computing applications.

关键词： PUFs low power security photonics

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Report on the 28th Asia and South Pacific design automation conference

IEEE DESIGN & TEST

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IEEE design & test 2023年第3期40卷 62-63页

作者： Takahashi, Atsushi Tokyo Inst Technol Meguro Ku Tokyo 1528550 Japan

The 28th Asia and South Pacific design automation conference (ASP-DAC 2023) was held at Miraikan, National Museum of Emerging Science and Innovation, Tokyo, Japan, 16 char6319 January 2023. ASP-DAC, started in 1995, is a high-quality and premium conference on Electronic design automation (EDA) like other sister conferences such as design automation conference (DAC); design, automation test in europe (DATE); International conference on Computer Aided design (ICCAD); and Embedded Systems Week (ESWEEK). ASP-DAC 2023 adopted an in-person conference style with online features which is the first time in ASP-DAC. Even though the last two ASP-DAC conferences were held as virtual conferences due to the COVID-19 pandemic, ASPDAC 2023 provided opportunities for face-to-face communication not only at sessions, but also at coffee breaks, banquet, and so on for in-person attendees. Online access mainly for participants who were difficult to physically attend was also provided as much as possible.

关键词： COVID-19 Technological innovation design automation Embedded systems Pandemics Asia europe

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DropHD: Technology/Algorithm Co-design for Reliable Energy-efficient NVM-based Hyperdimensional Computing under Voltage Scaling

DropHD: Technology/Algorithm Co-design for Reliable Energy-e...

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27th design, automation and test in europe conference and Exhibition (DATE)

作者： Genssler, Paul R. Mayahiniat, Mahta Thomann, Simon Tahoori, Mehdi B. Amrouch, Hussam Univ Stuttgart Semicond Test & Reliabil Stuttgart Germany Karlsruhe Inst Technol Dept Comp Sci & Informat Karlsruhe Germany Tech Univ Munich TUM Sch Computat Informat & Technol Chair AI Processor Design Munich Germany Munich Inst Robot & Machine Intelligence Munich Germany

ISBN: (纸本)9798350348606;9783981926385

Brain-inspired hyperdimensional computing (HDC) offers much more efficient computing compared to other classical deep learning and related machine learning algorithms. Unlike classical CMOS, emerging non-volatile memories (NVMs) used in the realization of HDC are susceptible to failures under voltage scaling, which is essential for energy saving. Although HDC is inherently robust against errors, this is only possible when hypervectors with a large dimension (e.g., 10,000 bits) are being used, resulting in significant energy consumption. This work demonstrates, for the first time, that different NVM technologies exhibit different error characteristics under voltage scaling. In contrast to conventional CMOS-based SRAM, we demonstrate that the error behavior is data-dependent and not captured by simple bit flips in emerging NVMs. We employ our cross-layer framework that starts from the underlying technology all the way up to the algorithm to develop the novel HDC training approach DropHD. DropHD considerably shrinks the size of hypervectors (e.g., from 10,000 bits down to merely 3000 bits), while maintaining a high inference accuracy. The use of aggressive voltage scaling reduces energy consumption by 1.6 x. DropHD further reduces it to up to 9.5 x while fully recovering the induced accuracy drop, i.e., without a tradeoff.

关键词： Hyperdimensional computing Non-volatile memory Content addressable memory (CAM) Voltage Scaling

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Compact test Pattern Generation For Multiple Faults In Deep Neural Networks

Compact Test Pattern Generation For Multiple Faults In Deep ...

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design, automation and test in europe conference and Exhibition (DATE)

作者： Moussa, Dina A. Hefenbrock, Michael Tahoori, Mehdi Karlsruhe Inst Technol Karlsruhe Germany RevoAI GmbH Karlsruhe Germany

ISBN: (纸本)9798350396249

Deep neural networks (DNNs) have achieved record-breaking performance in various applications. To reduce the energy footprint and increase performance, DNNs are often implemented on specific hardware accelerators, such as Tensor Processing Units (TPU) or emerging Memristive technologies. Unfortunately, the presence of various hardware faults can threaten these accelerators' performance and degrade the inference accuracy. This necessitates the development of efficient testing methodologies to unveil hardware faults in DNN accelerators. In this work, we propose a test pattern generation approach to detect fault patterns in DNNs for a common type of hardware fault, namely, faulty weight value representations on the bit level. Contrary to most related works which reveal faults via output deviations, our test patterns are constructed to reveal faults via misclassification which is more realistic for black-box testing.

关键词： Deep neural networks

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Device-Aware test for Back-Hopping Defects in STT-MRAMs

Device-Aware Test for Back-Hopping Defects in STT-MRAMs

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design, automation and test in europe conference and Exhibition (DATE)

作者： Yuan, Sicong Taouil, Mottaqiallah Fieback, Moritz Xun, Hanzhi Marinissen, Erik Jan Kar, Gouri Sankar Rao, Sidharth Couet, Sebastien Hamdioui, Said TUDelft Delft Netherlands CognitiveIC Delft Netherlands IMEC Leuven Belgium

ISBN: (纸本)9798350396249

The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH);it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms;the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations;new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a design-for-test solutions are proposed.

关键词： Defects

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On Decomposing Complex test Cases for Efficient Post-silicon Validation 24

On Decomposing Complex Test Cases for Efficient Post-silicon...

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29th Asia and South Pacific design automation conference (ASP-DAC)

作者： Harshitha, C. Harikrishna, Sundarapalli Rohith, Peddakotla Chandran, Sandeep Kalayappan, Rajshekar Indian Inst Technol Palakkad Kanjikode India Indian Inst Technol Dharwad Chikka Malligwad India

ISBN: (纸本)9798350393545

In post-silicon validation, the first step when an erroneous behavior is uncovered by a long-running test case is to reproduce the observed behavior in a shorter execution. This makes it amenable to use a variety of tools and techniques to debug the error. In this work, we propose a tool called Gru, that takes a long execution trace as input and generates a set of executables, one for each section of the trace. Each generated executable is guaranteed to faithfully replicate the behavior observed in the corresponding section of the original, complex test case independently. This enables the generated executables to be run simultaneously across different silicon samples, thereby allowing further debugging activities to proceed in parallel. The generation of executables does not require the source code of the complex test case and hence supports privacy-aware debugging in scenarios involving sensitive Intellectual Properties (IPs). We demonstrate the effectiveness of this tool on a collection of 10 EEMBC benchmarks that are executed on a bare-metal LEON3 SoC.

关键词： Silicon

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