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A Reduced overhead Accumulator-based BIST scheme for Two-pattern generation 9

A Reduced overhead Accumulator-based BIST scheme for Two-pat...

引用

9th South-East europe design automation, Computer Engineering, Computer Networks and Social Media conference, SEEDA-CECNSM 2024

作者： Fotopoulos, E. Fatouros, S. Milidonis, A. Voyiatzis, I. University of West Attica Department of Informatics and Computer Engineering Athens Greece

ISBN: (纸本)9798350342482

Two-pattern tests target the detection of common failure mechanisms in CMOS VLSI circuits, modelled as stuck-open or delay faults. In this paper, a Reduced-overhead Accumulator-Based BIST scheme for Two-pattern generation (RABIT) is presented, that generates an exhaustive n-bit two-pattern test. RABIT is implemented in hardware utilizing an accumulator whose inputs are driven by a binary counter. An important advantage of the presented scheme is that it can be implemented by augmenting existing data path components, rather than building a new pattern generation structure. Furthermore, with the proposed scheme, the requirement for additional (i.e. control and/or accompanying) circuitry is eliminated. Comparisons with previously proposed schemes reveal that the proposed here scheme presents lower hardware overhead for the implementation of the BIST structure. © 2024 IEEE.

关键词： Built-in self test

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Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive test

Countering Uncertainties in In-Memory-Computing Platforms wi...

引用

design, automation and test in europe conference and Exhibition (DATE)

作者： Eldebiky, Amro Zhang, Grace Li Li, Bing Tech Univ Munich Munich Germany Tech Univ Darmstadt Darmstadt Germany

ISBN: (纸本)9798350396249

In-memory-computing (IMC) has become an efficient solution for implementing neural networks on hardware. However, IMC platforms request weights in neural networks to be programmed to exact values. This is a very demanding task due to programming complexity, process variations, noise, as well as thermal effects. Accordingly, new methods should be introduced to counter such uncertainties. In this paper, we first discuss a method to train neural networks statistically with process variations modeled as correlated random variables. The statistical effect is incorporated in the cost function during training. Consequently, a neural network after statistical training becomes robust to uncertainties. To deal with variations and noise further, we also introduce a compensation method with extra layers for neural networks. These extra layers are trained offline again after the weights in the original neural network are determined to enhance the inference accuracy. Finally, we will discuss a method for testing the effect of process variations in an optical acceleration platform for neural networks. This optical platform uses Mach-Zehnder Interferometers (MZIs) to implement the multiply-accumulate operations. However, trigonometric functions in the transformation matrix of an MZI make it very sensitive to process variations. To address this problem, we apply a recursive test procedure to determine the properties of MZIs inside an optical acceleration module, so that process variations can be compensated accordingly to maintain the inference accuracy of neural networks.

关键词： Linear transformations

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Built-in Self-test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory

Built-in Self-Test and Built-in Self-Repair Strategies Witho...

引用

design, automation and test in europe conference and Exhibition (DATE)

作者： Tsai, Yu-Chih Ting, Wen-Chien Wang, Chia-Chun Chang, Chia-Cheng Liu, Ren-Shuo Natl Tsing Hua Univ Hsinchu Taiwan

ISBN: (纸本)9798350396249

This paper proposes built-in self-test (BIST) and built-in self-repair (BISR) strategies for computing in memory (CIM), including a novel test method and two repair schemes. They all focus on mitigating the impacts of inherent and inevitable CIM inaccuracy on convolution neural networks (CNNs). Regarding the proposed BIST strategy, it exploits the distributive law to achieve at-speed CIM tests without storing testing vectors or golden results. Besides, it can assess the severity of the inherent inaccuracies among CIM bitlines instead of only offering a pass/fail outcome. In addition to BIST, we propose two BISR strategies. First, we propose to slightly offset the dynamic range of CIM outputs toward the negative side to create a margin for negative noises. By not cutting CIM outputs off at zero, negative noises are preserved to cancel out positive noises statistically, and accuracy impacts are mitigated. Second, we propose to remap the bitlines of CIM according to our BIST outcomes. Briefly speaking, we propose to map the least noisy bitlines to be the MSBs. This remapping can be done in the digital domain without touching the CIM internals. Experiments show that our proposed BIST and BISR strategies can restore CIM to less than 1% Top-1 accuracy loss with slight hardware overhead.

关键词： computing in memory built-in self-test built-in self-repair accelerator convolutional neural networks

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SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI

SAFEXPLAIN: Safe and Explainable Critical Embedded Systems B...

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design, automation and test in europe conference and Exhibition (DATE)

作者： Abella, Jaume Perez, Jon Englund, Cristofer Zonooz, Bahram Giordana, Gabriele Donzella, Carlo Cazorla, Francisco J. Mezzetti, Enrico Serra, Isabel Brando, Axel Agirre, Irune Eizaguirre, Fernando Thanh Hai Bui Arani, Elahe Sarfraz, Fahad Balasubramaniam, Ajay Badar, Ahmed Bloise, Ilaria Feruglio, Lorenzo Cinelli, Ilaria Brighenti, Davide Cunial, Davide Barcelona Supercomp Ctr Barcelona Spain BRTA Ikerlan Technol Res Ctr Barcelona Spain RISE Res Inst Sweden Gothenburg Sweden Navinfo Europe Eindhoven Netherlands AIKO Srl Turin Italy Exida Dev Srl Turin Italy Exida Engn Srl Rovereto Italy

ISBN: (纸本)9798350396249

Deep Learning (DL) techniques are at the heart of most future advanced software functions in Critical Autonomous AI-based Systems (CAIS), where they also represent a major competitive factor. Hence, the economic success of CAIS industries (e.g., automotive, space, railway) depends on their ability to design, implement, qualify, and certify DL-based software products under bounded effort/cost. However, there is a fundamental gap between Functional Safety (FUSA) requirements on CAIS and the nature of DL solutions. This gap stems from the development process of DL libraries and affects high-level safety concepts such as (1) explainability and traceability, (2) suitability for varying safety requirements, (3) FUSA-compliant implementations, and (4) real-time constraints. As a matter of fact, the data-dependent and stochastic nature of DL algorithms clashes with current FUSA practice, which instead builds on deterministic, verifiable, and pass/fail test-based software. The SAFEXPLAIN project tackles these challenges and targets by providing a flexible approach to allow the certification - hence adoption - of DL-based solutions in CAIS building on: (1) DL solutions that provide end-to-end traceability, with specific approaches to explain whether predictions can be trusted and strategies to reach (and prove) correct operation, in accordance to certification standards;(2) alternative and increasingly sophisticated design safety patterns for DL with varying criticality and fault tolerance requirements;(3) DL library implementations that adhere to safety requirements;and (4) computing platform configurations, to regain determinism, and probabilistic timing analyses, to handle the remaining non-determinism.

关键词： Fault tolerance

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Signature Driven Post-Manufacture testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery 24

Signature Driven Post-Manufacture Testing and Tuning of RRAM...

引用

29th Asia and South Pacific design automation conference (ASP-DAC)

作者： Saha, Anurup Amarnath, Chandramouli Ma, Kwondo Chatterjee, Abhijit Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9798350393545

Resistive random access Memory (RRAM) based spiking neural networks (SNN) are becoming increasingly attractive for pervasive energy-efficient classification tasks. However, such networks suffer from degradation of performance (as determined by classification accuracy) due to the effects of process variations on fabricated RRAM devices resulting in loss of manufacturing yield. To address such yield loss, a two-step approach is developed. First, an alternative test framework is used to predict the performance of fabricated RRAM based SNNs using the SNN response to a small subset of images from the test image dataset, called the SNN response signature (to minimize test cost). This diagnoses those SNNs that need to be performance-tuned for yield recovery. Next, SNN tuning is performed by modulating the spiking thresholds of the SNN neurons on a layer-by-layer basis using a trained regressor that maps the SNN response signature to the optimal spiking threshold values during tuning. The optimal spiking threshold values are determined by an off-line optimization algorithm. Experiments show that the proposed framework can reduce the number of out-of-spec SNN devices by up to 54% and improve yield by as much as 8.6%.

关键词： Spiking Neural Network Yield Recovery Alternative test Post-manufacture Tuning

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A Fast test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver 24

A Fast Test Compaction Method for Commercial DFT Flow Using ...

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29th Asia and South Pacific design automation conference (ASP-DAC)

作者： Chao, Zhiteng Zhang, Xindi Huang, Junying Ye, Jing Cai, Shaowei Li, Huawei Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Processors Beijing Peoples R China Chinese Acad Sci Inst Software State Key Lab Comp Sci Beijing Peoples R China Univ Chinese Acad Sci Sch Comp Sci & Technol Beijing Peoples R China CASTEST Co Ltd Beijing Peoples R China

ISBN: (纸本)9798350393545

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by commercial ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary, and leverages a dedicated Pure-MaxSAT solver to re-compact the test patterns generated by commercial ATPG tools. We also observe that commercial ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the "n-detect" mode, leading to superior compaction efficacy. In experiments on ISCAS89, ITC99, and open-source RISC-V CPU benchmarks, our method achieves an average reduction of 21.58% and a maximum of 29.93% in test cycles evaluated by commercial tools while maintaining fault coverage. Furthermore, our approach demonstrates improved performance compared with existing methods.

关键词： static test compaction Pure-MaxSAT DFT ATPG

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Static Probability Analysis Guided RTL Hardware Trojan test Generation 23

Static Probability Analysis Guided RTL Hardware Trojan Test ...

引用

28th Asia and South Pacific design automation conference (ASP-DAC)

作者： Wang, Haoyi Zhou, Qiang Cai, Yici Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450397834

Directed test generation is an effective method to detect potential hardware Trojan (HT) in RTL. While the existing works are able to activate hard-to-cover Trojans by covering security targets, the effectiveness and efficiency of identifying the targets to cover are ignored. We propose a static probability analysis method for identifying the hard-to-active data channel targets and generating the corresponding assertions for the HT test generation. Our method could generate test vectors to trigger Trojans from Trusthub, DeTrust, and OpenCores in 1 minute and get 104.33X time improvement on average compared with the existing method.

关键词： Hardware security

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proceedings of the 2021 design, automation test in europe (DATE 2021)

Proceedings -Design, Automation and Test in Europe, DATE

引用

proceedings -design, automation and test in europe, DATE 2021年 2021-February卷 iii-v页

作者： Fummi, Franco O'Connor, Ian Universitá di Verona Italy Ecole Centrale de Lyon France

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Automatic test Pattern Generation and Compaction for Deep Neural Networks 23

Automatic Test Pattern Generation and Compaction for Deep Ne...

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28th Asia and South Pacific design automation conference (ASP-DAC)

作者： Moussa, Dina Hefenbrock, Michael Muech, Christopher Tahoori, Mehdi Karlsruhe Inst Technol KIT Karlsruhe Germany

ISBN: (纸本)9781450397834

Deep Neural Networks (DNNs) have gained considerable attention lately due to their excellent performance on a wide range of recognition and classification tasks. Accordingly, fault detection in DNNs and their implementations plays a crucial role in the quality of DNN implementations to ensure that their post-mapping and infield accuracy matches with model accuracy. This paper proposes a functional-level automatic test pattern generation approach for DNNs. This is done by generating inputs which causes misclassification of the output class label in the presence of single or multiple faults. Furthermore, to obtain a smaller set of test patterns with full coverage, a heuristic algorithm as well as a test pattern clustering method using K-means were implemented. The experimental results showed that the proposed test patterns achieved the highest label misclassification and a high output deviation compared to state-of-the-art approaches.

关键词： Deep Neural Networks Fault injection Functional Faults test pattern generation test compaction

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Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level

Learning-Oriented Reliability Improvement of Computing Syste...

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design, automation and test in europe conference and Exhibition (DATE)

作者： Ranjbar, Behnaz Klemme, Florian Genssler, Paul R. Amrouch, Hussam Jung, Jinhyo Dave, Shail So, Hwisoo Lee, Kyongwoo Shrivastava, Aviral Lin, Ji-Yung Weckx, Pieter Mishra, Subrat Catthoor, Francky Biswas, Dwaipayan Kumar, Akash Tech Univ Dresden CFAED Chair Processor Design Dresden Germany Univ Stuttgart Chair Semicond Test & Reliabil STAR Stuttgart Germany Yonsei Univ Seoul South Korea Arizona State Univ Sch Comp & Augmented Intelligence Tempe AZ USA IMEC Leuven Belgium Katholieke Univ Leuven Leuven Belgium

ISBN: (纸本)9798350396249

Due to technology scaling in modern computing platforms, the safety and reliability issues have increased tremendously, which often accelerate aging, lead to permanent faults, and cause unreliable execution of applications. Failure in some computing systems like avionics may cause catastrophic consequences. Therefore, managing reliability under all circumstances of stress and environmental changes is crucial in all abstraction layers, from application to transistor levels. Machine learning techniques are recently being employed for dynamic reliability estimation and optimization. They can adapt to varying workloads and system conditions. This paper presents reliability improvement approaches from multiple perspectives-from transistor-level to application-level-and discusses their effectiveness and limitations as well as open challenges.

关键词： Aging Cross-layer reliability Device and circuit reliability Dynamic reliability estimation Error mitigation Machine learning for systems Task scheduling Timing reliability

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