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HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast test Vector Generation 24

HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Tes...

引用

29th Asia and South Pacific design automation conference (ASP-DAC)

作者： Pandey, Shruti Jayadeva Sarangi, Smruti R. Indian Inst Technol Delhi Elect Engn New Delhi India

ISBN: (纸本)9798350393545

ML models are increasingly being used to increase the test coverage and decrease the overall testing time. This field is still in its nascent stage and up till now there were no algorithms that could match or outperform commercial tools in terms of speed and accuracy for large circuits. We propose an ATPG algorithm HybMT in this paper that finally breaks this barrier. Like sister methods, we augment the classical PODEM algorithm that uses recursive backtracking. We design a custom 2-level predictor that predicts the input net of a logic gate whose value needs to be set to ensure that the output is a given value (0 or 1). Our predictor chooses the output from among two first-level predictors, where the most effective one is a bespoke neural network and the other is an SVM regressor. As compared to a popular, state-of-the-art commercial ATPG tool, HybMT shows an overall reduction of 56.6% in the CPU time without compromising on the fault coverage for the EPFL benchmark circuits. HybMT also shows a speedup of 126.4% over the best ML-based algorithm while obtaining an equal or better fault coverage for the EPFL benchmark circuits.

关键词： Computer circuits

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Overcoming test Debt and Advancing Software Sustainability with Automated testing: A B2B Trading Platform Case Study 57

Overcoming Test Debt and Advancing Software Sustainability w...

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57th Hawaii International conference on System Sciences (HICSS)

作者： Zhang, Xiaoge Sharma, Bhavika Koppe, Timo Tech Univ Darmstadt Darmstadt Germany

ISBN: (纸本)9780998133171

This paper explores the current state of software quality assurance (SQA) practices with a focus on test automation. It applies these practices to a B2B online trading platform and builds a conceptual framework to implement automated end-to-end (E2E) tests for a critical business process and develop a test debt payback approach to increase unit test coverage. Our research follows the design Science Research (DSR) methodology and offers deep insights through collaboration with the business and development team. The paper concludes by providing strategical and operational recommendations for organizations looking to improve their SQA processes. Overall, the study highlights the importance of SQA and test automation for long-lasting software and demonstrates concrete approaches for solving common challenges in the field.

关键词： E2E testing test automation Sustainable Software test Debt Payback Case Study

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Error Generation for 3D NAND Flash Memory

Error Generation for 3D NAND Flash Memory

引用

25th design, automation and test in europe conference and Exhibition (DATE)

作者： Liu, Weihua Wu, Fei Meng, Songmiao Chen, Xiang Xie, Changsheng Minist Educ China Engn Res Ctr Data Storage Syst & Technol Key Lab Informat Storage Syst Wuhan Natl Lab Optoelect Wuhan Hubei Peoples R China

ISBN: (纸本)9783981926361

Three-dimension (3D) NAND flash memory is the preferred storage component of solid-state drive (SSD) for its high ratio of capacity and cost. Optimizing the reliability of modern SSD needs to test and collect a large amount of real-world error data from 3D NAND flash memory. However, the test costs have surged dozens of times as its capacity increases. It's imperative to reduce the costs of testing denser and high-capacity flash memory. To facilitate it, in this paper, we aim to enable reproducing error data efficiently for 3D NAND flash memory. We use a conditional generative adversarial network (cGAN) to learn the error distribution with multiple interferences and generate diverse error data comparable to the real-world. Evaluation results demonstrate it is feasible and efficient for error generation with cGAN.

关键词： test Generation 3D NAND flash memory Reliability

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Cyber-physical metropolitan area digital substations test bench for evaluating intrusion detection systems 6

Cyber-physical metropolitan area digital substations test be...

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6th Global Power, Energy and Communication conference (GPECOM)

作者： Sanchez-Acevedo, Santiago Zerihun, Tesfaye Amare Koshutanski, Hristo Garcia-Bedoya, Alejandro SINTEF Energy Res Dept Energy Syst Trondheim Norway Eviden BDS R&D Cybersecur Unit Madrid Spain

ISBN: (纸本)9798350351088;9798350351095

This paper introduces a cyber-physical test bench for metropolitan area digital substations, which serves as a platform for studying advanced cyber-attacks and evaluating intrusion detection systems. The test bench provides a hardware-in-the-loop environment with a high Technology Readiness Level (TRL). Additionally, the paper demonstrates the testbed's capabilities by testing and validating an AI-based intrusion detection system developed by an industrial company. The demonstration includes testing the cybersecurity tool against a wide range of cyber-attacks, such as false data injection, packet replay, and time desynchronization, on relevant substation automation protocols commonly used in EU power grid infrastructures like IEC-60870-5-104 and IEC61850. The results of the demonstration indicate that the test bench effectively simulates realistic impacts on substation operation when subjected to attacks, thus providing the opportunity to validate the anomaly detection solution.

关键词： Cyber-physical systems Intrusion detection systems Hardware-in-the-loop Smart grid Cyber security

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Intelligent Methods for test and Reliability

Intelligent Methods for Test and Reliability

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25th design, automation and test in europe conference and Exhibition (DATE)

作者： Amrouch, H. Anders, J. Becker, S. Betka, M. Bleher, G. Domanski, P. Elhamawy, N. Ertl, T. Gatzastras, A. Genssler, P. Hasler, S. Heinrich, M. van Hoorn, A. Jafarzadeh, H. Kallfass, I Klemme, F. Koch, S. Kuesters, R. Lalama, A. Latty, R. Liao, Y. Lylina, N. Haghi, Z. Najafi Pflueger, D. Polian, I Rivoir, J. Sauer, M. Schwachhofer, D. Templin, S. Volmer, C. Wagner, S. Weiskopf, D. Wunderlich, H-J Yang, B. Zimmermann, M. Univ Stuttgart Stuttgart Germany Advantest Corp Tokyo Japan

ISBN: (纸本)9783981926361

test methods that can keep up with the ongoing increase in complexity of semiconductor products and their underlying technologies are an essential prerequisite for maintaining quality and safety of our daily lives and for continued success of our economies and societies. There is a huge potential how test methods can benefit from recent breakthroughs in domains such as artificial intelligence, data analytics, virtual/augmented reality, and security. The Graduate School on "Intelligent Methods for Semiconductor test and Reliability" (GS-IMTR) at the University of Stuttgart is a large-scale, radically interdisciplinary effort to address the scientific-technological challenges in this domain. It is funded by Advantest, one of the world leaders in automatic test equipment. In this paper, we describe the overall philosophy of the Graduate School and the specific scientific questions targeted by its ten projects.

关键词： Philosophical considerations Data analysis Collaboration Reliability engineering Safety Manufacturing Complexity theory

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Improving Cell-Aware test for Intra-Cell Short Defects

Improving Cell-Aware Test for Intra-Cell Short Defects

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25th design, automation and test in europe conference and Exhibition (DATE)

作者： Lee, Dong-Zhen Chen, Ying-Yen Wu, Kai-Chiang Chao, Mango C-T Realtek Semicond Corp Hsinchu Taiwan Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu Taiwan Natl Yang Ming Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (纸本)9783981926361

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. In this paper, we propose to improve cell-aware (CA) test methodology by concentrating on intra-cell bridging faults due to short defects inside standard cells. The faults extracted are based on examining the actual physical proximity of polygons in the layout of a cell, and are thus more realistic and reasonable than those (faults) determined by RC extraction. Experimental results on a set of industrial designs show that the proposed methodology can indeed improve the test quality of intra-cell bridging faults. On average, 0.36% and 0.47% increases in fault coverage can be obtained for 1-time-frame and 2-time-frame CA tests, respectively. In addition to short defects between two metal polygons, short defects among three metal polygons are also considered in our methodology for another 9.33% improvement in fault coverage.

关键词： Layout Metals Behavioral sciences Circuit faults Integrated circuit modeling Standards Equivalent circuits

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Using Formal Conformance testing to Generate Scenarios for Autonomous Vehicles

Using Formal Conformance Testing to Generate Scenarios for A...

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25th design, automation and test in europe conference and Exhibition (DATE)

作者： Horel, Jean-Baptiste Laugier, Christian Marsso, Lina Mateescu, Radu Muller, Lucie Paigwar, Anshul Renzaglia, Alessandro Serwe, Wendelin Univ Grenoble Alpes Inria F-38000 Grenoble France Univ Toronto Dept Comp Sci Toronto ON Canada Univ Grenoble Alpes Inria CNRS Grenoble INPLIG F-38000 Grenoble France

ISBN: (纸本)9783981926361

Simulation, a common practice to evaluate autonomous vehicles, requires to specify realistic scenarios, in particular critical ones, occurring rarely and potentially dangerous to reproduce on the road. Such scenarios may be either generated randomly, or specified manually. Randomly generating scenarios is easy, but their relevance might be difficult to assess. Manually specified scenarios can focus on a given feature, but their design might be difficult and time-consuming, especially to achieve satisfactory coverage. In this work, we propose an automatic approach to generate a large number of relevant critical scenarios for autonomous driving simulators. The approach is based on the generation of behavioral conformance tests from a formal model (specifying the ground truth configuration with the range of vehicle behaviors) and a test purpose (specifying the critical feature to focus on). The obtained abstract test cases cover, by construction, all possible executions exercising a given feature, and can be automatically translated into the inputs of autonomous driving simulators. We illustrate our approach by generating thousands of behavior trees for the CARLA simulator for several realistic configurations.

关键词： Behavior trees CARLA simulator Formal methods Input-output conformance Scenario generation test purpose

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Report on the 28th Asia and South Pacific design automation conference

Report on the 28th Asia and South Pacific Design Automation ...

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作者： Takahashi, Atsushi Tokyo Institute of Technology Ookayama Meguro-ku Tokyo152-8550 Japan

The 28th Asia and South Pacific design automation conference (ASP-DAC 2023) was held at Miraikan, National Museum of Emerging Science and Innovation, Tokyo, Japan, 16 char6319 January 2023. ASP-DAC, started in 1995, is a high-quality and premium conference on Electronic design automation (EDA) like other sister conferences such as design automation conference (DAC);design, automation test in europe (DATE);International conference on Computer Aided design (ICCAD);and Embedded Systems Week (ESWEEK). ASP-DAC 2023 adopted an in-person conference style with online features which is the first time in ASP-DAC. Even though the last two ASP-DAC conferences were held as virtual conferences due to the COVID-19 pandemic, ASPDAC 2023 provided opportunities for face-to-face communication not only at sessions, but also at coffee breaks, banquet, and so on for in-person attendees. Online access mainly for participants who were difficult to physically attend was also provided as much as possible. © 2013 IEEE.

关键词： Computer aided design

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test Tube Assortment using SCARA Robot Platform 10

Test Tube Assortment using SCARA Robot Platform

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10th International conference on Control, automation and Robotic (ICCAR)

作者： Ashok, Anagha Jain, Chirag Relekar, Rajath J. Rajput, Raunak Venkatarangan, M. J. PES Univ Elect & Elect Bengaluru India PES Univ Dept Elect & Elect Bengaluru India

ISBN: (纸本)9798350373172;9798350373189

The Robotic system has been deployed for many applications that enable productivity. Out of many robots, the Selective Compliance Assembly Robot Arm (SCARA) stands off as it is faster than most industrial robots. SCARA robots have the best positional repeatability among all industrial robots. This SCARA robot platform, recognized for its precision and versatility, is designed for assorting test tubes in a laboratory, involving the construction of a robot for picking and placing test tubes. The SCARA robot is built based on a mechanical open design with all the adaptations needed for the application mainly on dimensions, end-effector etc using Fusion360. The actuators were based on four NEMA17 stepper motors and one servo exclusively for the end effector. The actuators were driven with an A4988 driver from an Arduino microcontroller;the power source was a computer power supply. The modelling of the robot is undertaken based on Denavit-Hartenburg (DH) parameters to formulate the kinematics. The inverse kinematics implementation in the software enabled the pick and place operations as part of the application. The system features positional control and an articulated arm structure, contributing to its effectiveness. testing was done using a 6-hole wooden platform where test tubes were sorted according to a given input. The robot swiftly and accurately picks up from home and places it into one of the six holes for assortment. The experimental results demonstrate the transformative impact of SCARA robots in this application, enhancing productivity and accuracy.

关键词： SCARA NEMA17 Arduino 3D Printing test Tube ROS

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Guaranteed Activation of Capacitive Trojan Triggers During Post Production test via Supply Pulsing

Guaranteed Activation of Capacitive Trojan Triggers During P...

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25th design, automation and test in europe conference and Exhibition (DATE)

作者： Bilgic, Bora Ozev, Sule Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA

ISBN: (纸本)9783981926361

Involvement of many parties in the production of integrated circuits (ICs) makes the process more vulnerable to tampering. Consequently, IC security has become an important challenge to tackle. One of the threat models in hardware security domain is the insertion of unwanted and malicious hardware components, known as Hardware Trojans (HTs). A malicious attacker can insert a small modification into the functional circuit that can cause havoc in the field. To make the Trojan circuit stealthy, trigger circuits are typically used. The purpose of the trigger circuit is to hide the Trojan activity during post-production testing, and to randomize activation conditions, thereby making it very difficult to diagnose even after failures. Trigger mechanisms for Trojans typically delay and randomize the outcome based on a subset of internal digital signals. While there are many different ways of implementing the trigger mechanisms, charge based mechanisms have gained popularity due to their small size. In this paper, we propose a scheme to ensure that the trigger mechanisms are activated during production testing even if the conditions specified by the malicious attacker are not met. By disabling the mechanism that makes the Trojan stealthy, any of the parametric techniques can be used to detect Trojans at production time. The proposed technique relies on supply pulsing, where an increased potential difference between the gate and bulk of the active transistor in the output stage generates an alternate charge path for an otherwise unreachable capacitor and bypasses the input conditions to the trigger mechanism. SPICE simulations show that our method works well even for the smallest Trojan trigger mechanisms.

关键词： analog charge domain Trojan capacitor security detection

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