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Late Breaking Results: test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation 60

Late Breaking Results: Test Selection For RTL Coverage By Un...

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60th ACM/IEEE design automation conference (DAC)

作者： Liang, Rongjian Pinckney, Nathaniel Chai, Yuji Ren, Haoxin Khailany, Brucek NVIDIA Austin TX 78717 USA Harvard Univ Dept Comp Sci Cambridge MA 02138 USA

ISBN: (纸本)9798350323481

Functional coverage closure is an important but RTL simulation intensive aspect of constrained random verification. To reduce these computational demands, we propose test selection for functional coverage via machine learning (ML) based anomaly detection in the structural coverage space of fast functional simulators. We achieve promising results on two units from a state-of-the-art production GPU design. With our approach, an up to 85% RTL simulation runtime reduction can be achieved when compared to baseline constrained random test selection while achieving the same RTL functional coverage.

关键词： Anomaly detection

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proceedings of the 2021 design, automation & test in europe (DATE 2021)

Proceedings of the 2021 Design, Automation & Test in Europe ...

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design, automation and test in europe conference and Exhibition

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright ©2021 by IEEE.

关键词： design automation europe Security Industries conferences Tutorials Tools

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Bit-accurate RTL simulation of an NQR spectrometer's SoC-FPGA 31

Bit-accurate RTL simulation of an NQR spectrometer's SoC-FPG...

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31st conference on Electronics Circuits and Systems

作者： Kachkachi, Nor Eddine Rabah, Hassan CNRS CRM2 F-54000 Nancy France Univ Lorraine IJL F-54000 Nancy France

ISBN: (纸本)9798350377217;9798350377200

This paper presents a comprehensive verification environment and methodology for fully verifying a System on Chip-Field-Programmable Gate Array (SoC-FPGA) used in building an NQR spectrometer through RTL simulation. The verification environment includes an RTL testbench, a database of tests, design modules simulation models, and simulation automation scripts. Initially, the system is simulated in an RTL testbench written in System Verilog, with the SoC-FPGA as the Device Under test (DUT). To simulate real NMR/NQR experiments, various tests are created, each corresponding to a specific experiment, comprising stimuli, current test configuration files and reference files. For each test, the simulation output files of the DUT are compared bit-wise to the reference files. Simulation and check scripts provide a snapshot of the design's non-regression status. This methodology and platform enable in-depth verification of the SoC-FPGA's functionality, significantly reducing the experimental validation time of the NQR spectrometer on real samples. Future enhancements could include verifying the signal denoising algorithms implemented on the SoC-FPGA.

关键词： NQR NMR Spectrometer Verification SoC-FPGA RTL Simulation Reference automation Scripting test

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ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors all the Way up Processors 23

ML to the Rescue: Reliability Estimation from Self-Heating a...

引用

28th Asia and South Pacific design automation conference (ASP-DAC)

作者： Amrouch, Hussam Klemme, Florian Univ Stuttgart Chair Semicond Test & Reliabil STAR Stuttgart Germany

ISBN: (纸本)9781450397834

With increasingly confined 3D structures and newly-adopted materials ofhigher thermal resistance, transistor self-heating has risen to a critical reliability threat in state-of-the-art and emerging process nodes. One of the challenges of transistor self-heating is accelerated transistor aging, which leads to earlier failure of the chip if not considered appropriately. Nevertheless, adequate consideration of accelerated aging effects, induced by self-heating, throughout a large circuit design is profoundly challenging due to the large gap between where self-heating does originate (i.e., at the transistor level) and where its ultimate effect occurs (i.e., at the circuit and system levels). In this work, we demonstrate an end-to- end workflow starting from self-heating and aging effects in individual transistors all the way up to large circuits and processor designs. We demonstrate that with our accurately estimated degradations, the required timing guardband to ensure reliable operation of circuits is considerably reduced by up to 96 % compared to otherwise worst-case estimations that are conventionally employed.

关键词： Circuit reliability transistor self-heating transistor aging machine learning library characterization CAD

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Low-Complexity Algorithmic test Generation for Neuromorphic Chips 24

Low-Complexity Algorithmic Test Generation for Neuromorphic ...

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61st ACM/IEEE design automation conference, DAC 2024

作者： Huang, Hsu-Yu Hsiao, Chu-Yun Liu, Tsung-Te Li, James Chien-Mo National Taiwan University Taipei Taiwan

ISBN: (纸本)9798400706011

Neuromorphic chips are promising hardware implementations for artificial intelligence (AI) applications owing to their low power consumption. However, neuromorphic chips are difficult to test since they have many potential configurations but lack design for testability (DfT). We propose an algorithmic test generation method for neuromorphic chips without DfT, including fault activation and fault propagation. Fault activation differentiates a neuron's good output and faulty output. Fault propagation sensitizes fault effects to differentiate outputs of faulty chips and good chips. On an L-layer Spiking Neural Network (SNN) model, we achieve 100% fault coverage using O(L) test configurations and test patterns under negligible or no weight variation. Our results show that test effectiveness is maintained even with 4-bit weight quantization. We incur no test escape and overkill even under 10% weight variation. Our total test length is over 73K times shorter than previous works. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： design for testability

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Late Breaking Results: Efficient Built-in Self-test for Microfluidic Large-Scale Integration (mLSI) 24

Late Breaking Results: Efficient Built-in Self-Test for Micr...

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61st ACM/IEEE design automation conference, DAC 2024

作者： Li, Mengchu Gu, Hanchen Zhang, Yushen Liang, Siyuan Gasvoda, Hudson Altay, Rana Araci, Ismail Emre Tseng, Tsun-Ming Ho, Tsung-Yi Schlichtmann, Ulf Technical University of Munich Germany ETH Zurich Switzerland The Chinese University of Hong Kong Hong Kong Santa Clara University United States

ISBN: (纸本)9798400706011

Control channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. In this work, we propose a built-in self-test (BIST) method that drastically improves the test efficiency. Given n to-be-tested control channels, we reduced the number of test patterns for blockage and leakage tests from ⌈n/2 ⌉ to 1, and from ⌈log2(n + 1)⌉ to ⌈log2 (χ (G) + 1)⌉, respectively, where χ(G) denotes the vertex chromatic number of a graph G consisting of n vertices. We fabricated our design and demonstrated the feasibility and efficiency of our method. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Microfluidics

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Coverage-based Strategies for the Automated Synthesis of test Scenarios for Conversational Agents 5

Coverage-based Strategies for the Automated Synthesis of Tes...

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5th IEEE/ACM International conference on automation of Software test (AST)

作者： Canizares, Pablo C. Avila, Daniel Perez-Soler, Sara Guerra, Esther de lara, Juan Univ Autonoma Madrid Madrid Spain

ISBN: (纸本)9798400705885

Conversational agents - or chatbots - are increasingly used as the user interface to many software services. While open-domain chatbots like ChatGPT excel in their ability to chat about any topic, task-oriented conversational agents are designed to perform goaloriented tasks (e.g., booking or shopping) guided by a dialoguebased user interaction, which is explicitly designed. Like any kind of software system, task-oriented conversational agents need to be properly tested to ensure their quality. For this purpose, some tools permit defining and executing conversation test cases. However, there are currently no established means to assess the coverage of the design of a task-oriented agent by a test suite, or mechanisms to automate quality test case generation ensuring the agent coverage. To attack this problem, we propose test coverage criteria for task-oriented conversational agents, and define coverage-based strategies to synthesise test scenarios, some oriented to test case reduction. We provide an implementation of the criteria and the strategies that is independent of the agent development platform. Finally, we report on their evaluation on open-source Dialogflow and Rasa agents, and a comparison against a state-of-the-art testing tool. The experiment shows benefits in terms of test generation correctness, increased coverage and reduced testing time.

关键词： testing test suite generation Task-oriented conversational agents

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design and verification of self-adaptive control towing apparatus for ship model test 4

Design and verification of self-adaptive control towing appa...

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4th International conference on Mechanical, Electronics, and Electrical and automation Control, METMS 2024

作者： Wu, Yongshun Huang, Lei Le, Yan Li, Dehai Yang, Sujun Marine Design & Research Institute of China Shanghai China Shanghai Key Laboratory of Ship Engineering Shanghai China Laboratory of Science and Technology on Water Jet Shanghai China

ISBN: (数字)9781510679887

ISBN: (纸本)9781510679870

According to International Towing Tank conference (ITTC) corresponding guidelines and rules, ship model test is vital for the determination on overall performance of the ship. In order to study ship speed performance, it is necessary to accurately determine its resistance in model scale. And during the test, an appropriate towing installation is very important because of its effecting on the heave and longitudinal angle of ship mode, which is the main factor of the resistance. Combined with the latest test equipment and control technologies, a self-adaptive control towing device design, resistance and posture measurement and control principle were studied, a towing system suitable for high-speed boat resistance test was developed, and the advantages of the system were analyzed. Based on this, and a standard planning craft model test is applied, which can verify the validity of installation. © 2024 SPIE.

关键词： Adaptive control systems

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SHarPen: SoC Security Verification by Hardware Penetration test 23

SHarPen: SoC Security Verification by Hardware Penetration T...

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28th Asia and South Pacific design automation conference (ASP-DAC)

作者： Al-Shaikh, Hasan Vafaei, Arash Rahman, Mridha Md Mashahedur Azar, Kimia Zamiri Rahman, Fahim Farahmandi, Farimah Tehranipoor, Mark Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781450397834

As modern SoC architectures incorporate many complex/heterogeneous intellectual properties (IPs), the protection of security assets has become imperative, and the number of vulnerabilities revealed is rising due to the increased number of attacks. Over the last few years, penetration testing (PT) has become an increasingly effective means of detecting software (SW) vulnerabilities. As of yet, no such technique has been applied to the detection of hardware vulnerabilities. This paper proposes a PT framework, SHarPen, for detecting hardware vulnerabilities, which facilitates the development of a SoC-level security verification framework. SHarPen proposes a formalism for performing gray-box hardware (HW) penetration testing instead of relying on coverage-based testing and provides an automation for mapping hardware vulnerabilities to logical/mathematical cost functions. SHarPen supports both simulation and FPGA-based prototyping, allowing us to automate security testing at different stages of the design process with high capabilities for identifying vulnerabilities in the targeted SoC.

关键词： SoC Security Verification Penetration testing BPSO Cost Function

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Unsupervised test-Time Adaptation of Deep Neural Networks at the Edge: A Case Study

Unsupervised Test-Time Adaptation of Deep Neural Networks at...

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25th design, automation and test in europe conference and Exhibition (DATE)

作者： Bhardwaj, Kshitij Diffenderfer, James Kailkhura, Bhavya Gokhale, Maya Lawrence Livermore Natl Lab Livermore CA 94550 USA

ISBN: (纸本)9783981926361

Deep learning is being increasingly used in mobile and edge autonomous systems. The prediction accuracy of deep neural networks (DNNs), however, can degrade after deployment due to encountering data samples whose distributions are different than the training samples. To continue to robustly predict, DNNs must be able to adapt themselves post-deployment. Such adaptation at the edge is challenging as new labeled data may not be available, and it has to be performed on a resource-constrained device. This paper performs a case study to evaluate the cost of test-time fully unsupervised adaptation strategies on a real-world edge platform: Nvidia Jetson Xavier NX. In particular, we adapt pretrained state-of-the-art robust DNNs (trained using data augmentation) to improve the accuracy on image classification data that contains various image corruptions. During this prediction-time on-device adaptation, the model parameters of a DNN are updated using a single backpropagation pass while optimizing entropy loss. The effects of following three simple model updates are compared in terms of accuracy, adaptation time and energy: updating only convolutional (Conv-Tune);only fully-connected (FC-Tune);and only batch-norm parameters (BN-Tune). Our study shows that BN-Tune and Conv-Tune are more effective than FC-Tune in terms of improving accuracy for corrupted images data (average of 6.6%, 4.97%, and 4.02%, respectively over no adaptation). However, FC-Tune leads to significantly faster and more energy efficient solution with a small loss in accuracy. Even when using FC-Tune, the extra overheads of on-device fine-tuning are significant to meet tight real-time deadlines (209ms). This study motivates the need for designing hardware-aware robust algorithms for efficient ondevice adaptation at the autonomous edge.

关键词： Robust deep learning on-device neural network adaptation unsupervised adaptation edge devices

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