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检索条件"任意字段=Proceedings of the Conference on Parallel Architectures and Compilation Techniques"

共 1660 条记录，以下是91-100 订阅

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HBMax: Optimizing Memory Efficiency for parallel Influence Maximization on Multicore architectures 22

HBMax: Optimizing Memory Efficiency for Parallel Influence M...

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Xinyu Chen Marco Minutoli Jiannan Tian Mahantesh Halappanavar Ananth Kalyanaraman Dingwen Tao Washington State University Pacific Northwest National Laboratory Indiana University

ISBN: (纸本)9781450398688

Influence maximization aims to select k most-influential vertices or seeds in a network, where influence is defined by a given diffusion process. Although computing optimal seed set is NP-Hard, efficient approximation algorithms exist. However, even state-of-the-art parallel implementations are limited by a sampling step that incurs large memory footprints. This in turn limits the problem size reach and approximation quality. In this work, we study the memory footprint of the sampling process collecting reverse reachability information in the IMM (Influence Maximization via Martingales) algorithm over large real-world social networks. We present a memory-efficient optimization approach (called HBMax) based on Ripples, a state-of-the-art multi-threaded parallel influence maximization solution. Our approach, HBMax, uses a portion of the reverse reachable (RR) sets collected by the algorithm to learn the characteristics of the graph. Then, it compresses the intermediate reverse reachability information with Huffman coding or bitmap coding, and queries on the partially decoded data, or directly on the compressed data to preserve the memory savings obtained through compression. Considering a NUMA architecture, we scale up our solution on 64 CPU cores and reduce the memory footprint by up to 82.1% with average 6.3% speedup (encoding overhead is offset by performance gain from memory reduction) without loss of accuracy. For the largest tested graph Twitter7 (with 1.4 billion edges), HBMax achieves 5.9× compression ratio and 2.2× speedup.

关键词： compression multicore architectures influence maximization

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parallel architectures and compilation techniques - conference proceedings, PACT

Parallel Architectures and Compilation Techniques - Conferen...

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25th International conference on parallel architectures and compilation techniques, PACT 2016

The proceedings contain 52 papers. The topics discussed include: combating the reliability challenge of GPU register file at low supply voltage;scheduling techniques for GPU architectures with processing-in-memory capabilities;OAWS: memory occlusion aware warp scheduling;integrating algorithmic parameters into benchmarking and design space exploration in 3D scene understanding;fusion of parallel array operations;reduction drawing: language constructs and polyhedral compilation for reductions on GPUs;accelerating linked-list traversal through near-data processing;scalable task parallelism for NUMA: a uniform abstraction for coordinated scheduling and memory management;and greater performance and better efficiency: predicated execution has shown us the way.

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A CPU-FPGA Holistic Source-To-Source compilation Approach for Partitioning and Optimizing C/C++ Applications 23

A CPU-FPGA Holistic Source-To-Source Compilation Approach fo...

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proceedings of the 32nd International conference on parallel architectures and compilation techniques

作者： Tiago Santos João Bispo João M. P. Cardoso Univ. of Porto FEUP and INESC-TEC Porto Portugal

ISBN: (纸本)9798350342543

A common approach for improving performance uses FPGAs to accelerate critical code regions, which often involves two processes: hardware/software partitioning, which identifies regions to offload to the FPGA; and optimizing those regions (e.g., through HLS directives). As both processes are separate and usually applied in sequence, the interplay between them is unnatural, and it is unclear how the choices made in one step can benefit the choices made in the other step. This paper presents our work-in-progress for combining partitioning and optimization into a single holistic process. First, our source-to-source compiler builds a task-based representation from the input application. Then, a greedy algorithm builds clusters of tasks and assigns each cluster to either hardware (FPGA) or software (CPU). The algorithm iteratively refines the clusters and offloading decisions by: a) minimizing the communication costs between clusters by assigning tasks that work with shared data to the same cluster; b) reducing the global execution time by applying code optimizations to the tasks in each cluster. We show the impact of our holistic approach to a motivating edge detection example and compare the results when applying partitioning and code optimizations as independent steps. The results show that a holistic partitioning can lead to a speedup of up to 28.7× when compared to a simple offloading of the application to an FPGA.

关键词： FPGA

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GPU Adaptive In-situ parallel Analytics (GAP) 22

GPU Adaptive In-situ Parallel Analytics (GAP)

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Haoyuan Xing Gagan Agrawal Rajiv Ramnath The Ohio State University Augusta University

ISBN: (纸本)9781450398688

Despite the popularity of in-situ analytics in scientific computing, there is only limited work to date on in-situ analytics for simulations running on GPUs. Notably, two unaddressed challenges are 1) performing memory-efficient in-situ analysis on accelerators and 2)automatically choosing the processing resources and suitable data representation for a given query and platform. This paper addresses both problems. First, GAP makes several new contributions toward making bitmap indices suitable, effective, and efficient as a compressed data summary structure for the GPUs - this includes introducing a layout structure, a method for generating multi-attribute bitmaps, and novel techniques for bitmap-based processing of major operators that comprise complex data analytics. Second, this paper presents a performance modeling methodology, aiming to predict the placement (i.e., CPU or GPU) and the data representation choice (summarization or original) that yield the best performance on a given configuration. Our extensive evaluation of complex in-situ queries and real-world simulations shows that with our methods, analytics on GPU using bitmaps almost always outperforms other options, and the GAP performance model predicts the optimal placement and data representation for most scenarios.

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BOLT: Optimizing OpenMP parallel Regions with User-Level Threads 19

BOLT: Optimizing OpenMP Parallel Regions with User-Level Thr...

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Shintaro Iwasaki Abdelhalim Amer Kenjiro Taura Sangmin Seo Pavan Balaji The University of Tokyo Tokyo Japan Argonne National Laboratory Lemont Illinois USA

ISBN: (纸本)9781728136134

OpenMP is widely used by a number of applications, computational libraries, and runtime systems. As a result, multiple levels of the software stack use OpenMP independently of one another, often leading to nested parallel regions. Although exploiting such nested parallelism is a potential opportunity for performance improvement, it often causes destructive performance with leading OpenMP runtimes because of their reliance on heavyweight OS-level threads. User-level threads (ULTs) are more lightweight alternatives but existing ULT-based runtimes suffer from several shortcomings: 1) thread management costs remain significant and outweigh the benefits from additional parallelism; 2) the shift to ULTs often hurts the more common flat parallelism case; and 3) absence of user control over thread-to-CPU binding, a critical feature on modern *** paper presents BOLT, a practical ULT-based OpenMP runtime system that efficiently supports both flat and nested parallelism. This is accomplished on three fronts: 1) advanced data reuse and thread synchronization strategies; 2) thread coordination that adapts to the level of oversubscription; and 3) an implementation of the modern OpenMP thread-to-CPU binding interface tailored to ULT-based runtimes. The result is a highly optimized runtime that transparently achieves similar performance compared with leading state-of-the-art widely used OpenMP runtimes under flat parallelism, while outperforming all existing runtimes under nested parallelism.

关键词： Multithreading

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Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations 22

Custom High-Performance Vector Code Generation for Data-Spec...

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proceedings of the International conference on parallel architectures and compilation techniques

作者： Marcos Horro Louis-Noël Pouchet Gabriel Rodríguez Juan Touriño Universidade da Coruña A Coruña Spain Colorado State University

ISBN: (纸本)9781450398688

Sparse computations, such as sparse matrix-dense vector multiplication, are notoriously hard to optimize due to their irregularity and memory-boundedness. Solutions to improve the performance of sparse computations have been proposed, ranging from hardware-based such as gather-scatter instructions, to software ones such as generalized and dedicated sparse formats, used together with specialized executor programs for different hardware targets. These sparse computations are often performed on read-only sparse structures: while the data themselves are variable, the sparsity structure itself does not change. Indeed, sparse formats such as CSR have a typically high cost to insert/remove nonzero elements in the representation. The typical use case is to not modify the sparsity during possibly repeated computations on the same sparse *** this work, we exploit the possibility to generate a specialized executor program dedicated to the particular sparsity structure of an input matrix. It creates opportunities to remove indirection arrays and synthesize regular, vectorizable code for such computations. But, at the same time, it introduces challenges in code size and instruction generation, as well as efficient SIMD vectorization. We present novel techniques and extensive experimental results to efficiently generate SIMD vector code for data-specific sparse computations, and study the limits in terms of applicability and performance of our techniques compared to state-of-practice high-performance libraries like Intel MKL.

关键词： sparse data structure data-specific compilation vectorization

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Memory-Equipped Quantum architectures: The Power of Random Access 20

Memory-Equipped Quantum Architectures: The Power of Random A...

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Baker, Jonathan M. Schuster, David, I Chong, Frederic T. Univ Chicago Chicago IL 60637 USA

ISBN: (纸本)9781450380751

Resonant cavities can be used to extend conventional superconducting transmon-based quantum architectures by adding a few bits of quantum memory to each transmon. Such architectures leverage the long coherence times of cavities creating a "memory-equipped" quantum architecture (MEQC) extending the amount of quantum state a machine can manipulate. However, random access to data will have the greatest effect on improving machine performance. Existing transmon architectures are locally connected and performing gates between distant qubits requires expensive pairwise swaps for execution. Added swap operations increase the probability of errors by increasing both operation count and execution time. We develop a complete compilation framework with heuristics to optimize for the load-store execution model of MEQC. We reduce the gate count and depth of compiled quantum programs by an average 1.62x and 1.70x, respectively compared to traditional transmon architectures. Based on small noise simulations, MEQC architectures outperform on programs as small as 10 qubits, and in general the probability of no gate errors, dominant in NISQ era, is greater on MEQC. If idle errors become more significant, MEQC will have a greater advantage. We conclude with an exploration of different architectural choices, such as transmon-transmon connectivity and cavity size, and explore their effect on the performance of the proposed architecture. While we expect due to small initial physical experiments that we have O(10) modes per cavity, the particular choice of cavity size in this 2.5D architecture is an important one. For example, when coherence times are high and we can withstand greater serialization it becomes more advantageous to favor larger cavity sizes. In the early stages of these devices, we expect transmon-transmon interactions to be potentially more expensive than transmon-cavity interactions. Our proposed solution can tolerate potentially up to 12x worse interconnect error.

关键词： quantum computing compilers computer architecture

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parallel and Scalable Precise Clustering 20

Parallel and Scalable Precise Clustering

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ACM International conference on parallel architectures and compilation techniques (PACT)

作者： Byma, Stuart Dhasade, Akash Altenhoff, Adrian Dessimoz, Christophe Larus, James R. Ecole Polytech Fed Lausanne Lausanne Switzerland IIT Tirupati Tirupati Andhra Pradesh India Swiss Fed Inst Technol Zurich Switzerland Univ Lausanne Lausanne Switzerland

ISBN: (纸本)9781450380751

This paper describes a new technique for parallelizing protein clustering, an important bioinformatics computation for the analysis of protein sequences. Protein clustering identifies groups of proteins that are similar because they share long sequences of similar amino acids. Given a collection of protein sequences, clustering can significantly reduce the computational effort required to identify all similar sequences by avoiding many negative comparisons. The challenge, however, is to build a clustering that misses as few similar sequences (or elements, more generally) as possible. In this paper, we introduce precise clustering, a property that requires each pair of similar elements to appear together in at least one cluster. We show that transitivity in the data can be leveraged to merge clusters while maintaining a precise clustering, providing a basis for independently forming clusters. This allows us reformulate clustering as a bottom-up merge of independent clusters in a new algorithm called ClusterMerge. ClusterMerge exposes parallelism, enabling fast and scalable implementations. We apply ClusterMerge to find similar amino acid sequences in a collection of proteins. ClusterMerge identifies 99.8% of similar pairs found by a full O(n(2)) comparison, with only half as many comparisons. More importantly, ClusterMerge is highly amenable to parallel and distributed computation. Our implementation achieves a speedup of 604 times on 768 cores (1400 times faster than a comparable single-threaded clustering implementation), a strong scaling efficiency of 90%, and a weak scaling efficiency of nearly 100%.

关键词： bioinformatics protein clustering parallel algorithms

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Towards Automatic Block Size Tuning for Image Processing Algorithms on CUDA

Towards Automatic Block Size Tuning for Image Processing Alg...

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17th International conference on Software Technologies (ICSOFT)

作者： Guerfi, Imene Kriaa, Lobna Saidane, Leila Azouz Univ Manouba Natl Sch Comp Sci ENSI CRISTAL Lab RAMSIS Pole Manouba Tunisia

ISBN: (纸本)9789897585883

With the growing amount of data, computational power has became highly required in all fields. To satisfy these requirements, the use of GPUs seems to be the appropriate solution. But one of their major setbacks is their varying architectures making writing efficient parallel code very challenging, due to the necessity to master the GPU's low-level design. CUDA offers more flexibility for the programmer to exploit the GPU's power with ease. However, tuning the launch parameters of its kernels such as block size remains a daunting task. This parameter requires a deep understanding of the architecture and the execution model to be well-tuned. Particularly, in the Viola-Jones algorithm, the block size is an important factor that improves the execution time, but this optimization aspect is not well explored. This paper aims to offer the first steps toward automatically tuning the block size for any input without having a deep knowledge of the hardware architecture, which ensures the automatic portability of the performance over different GPUs architectures. The main idea is to define techniques on how to get the optimum block size to achieve the best performance. We pointed out the impact of using static block size for all input sizes on the overall performance. In light of the findings, we presented two dynamic approaches to select the best block size suitable to the input size. The first one is based on an empirical search;this approach provides the optimal performance;however, it is tough for the programmer, and its deployment is time-consuming. In order to overcome this issue, we proposed a second approach, which is a model that automatically selects a block size. Experimental results show that this model can improve the execution time by up to 2.5x over the static approach.

关键词： GPU Computing parallel Programming Program Optimization Auto-tuning and Face Detection

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32nd International conference on Flexible Automation and Intelligent Manufacturing, FAIM 2023

32nd International Conference on Flexible Automation and Int...

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32nd International conference on Flexible Automation and Intelligent Manufacturing, FAIM 2023

ISBN: (纸本)9783031382406

The proceedings contain 239 papers. The special focus in this conference is on . The topics include: A Review of Value Stream Mapping (VSM) for Viable Business Process Management Among Agro-Allied Companies During the 4IR;outsourcing Optimization in Footwear Industry: The Case of a Portuguese Company;UWB-Based Indoor Navigation in a Flexible Manufacturing System Using a Custom Quadrotor UAV;real-Time Defect and Object Detection in Assembly Line: A Case for In-Line Quality Inspection;Using Computer Vision to Improve SME Performance;Cyber-Physical Systems Based Smart Manufacturing of Disinfectants: A Need, and Solution Driven by COVID-19 Pandemic;CPPS-3D: A Methodology to Support Cyber Physical Production Systems Design, Development and Deployment;reinforcement Learning-Based Model for Optimization of Cloud Manufacturing-Based Multi Objective Resource Scheduling: A Review;an Overview of Explainable Artificial Intelligence in the Industry 4.0 Context;Analyzing the Effects of Different 3D-Model Acquisition Methods for Synthetic AI Training Data Generation and the Domain Gap;improving Regulations for Automated Design Checking Through Decision Analysis Good Practices: A Conceptual Application to the Construction Sector;environment for the Design and Automation of New Cable-Driven parallel Robot architectures;preliminary Design of an Automatic Palletizing System During the Pre-sales Stage;a New Equipment for Automatic Calibration of the Semmes-Weinstein Monofilament;measuring the Moment-Curvature Relationship of a Steerable Catheter Using a Load Cell and Stereovision System;study of the Best Operational Parameters in Laser Marking of Plastic Parts;Laser Marking on White-Coloured Polyoxymethylene (POM) Polymer Substrate: Challenges and Perspectives;influence of Laser Beam Intensity Distribution on Keyhole Geometry and Process Stability Using Green Laser Radiation;advanced Characterization techniques of Multi-material Machining Tool Coatings.

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